5.7 Microcontroller Subsystem (MSS)
(Ask a Question)| Name | Type | Polarity/ Bus Size | Description |
|---|---|---|---|
| External Memory Controller | |||
| EMC_ABx | Out | 26 | External memory controller address bus Can also be used as an FPGA user I/O (see IO). |
| EMC_BYTENx | Out | LOW/2 | External memory controller byte enable Can also be used as an FPGA user I/O (see IO). |
| EMC_CLK | Out | Rise | External memory controller clock Can also be used as an FPGA user I/O (see IO). |
| EMC_CSx_N | Out | LOW/2 | External memory controller chip selects Can also be used as an FPGA User IO (see IO ). |
| EMC_DBx | In/out | 16 | External memory controller data bus Can also be used as an FPGA user I/O (see IO). |
| EMC_OENx_N | Out | LOW/2 | External memory controller output enables Can also be used as an FPGA User IO (see IO). |
| EMC_RW_N | Out | Level | External memory controller read/write. Read =
High, write = Low. Can also be used as an FPGA user I/O (see IO). |
| Inter-Integrated Circuit (I2C) Peripherals | |||
| I2C_0_SCL | In/out | 1 | I2C bus serial
clock output. First I2C. Can also be used as an MSS GPIO (see GPIO). |
| I2C_0_SDA | In/out | 1 | I2C bus serial
data input/output. First I2C. Can also be used as an MSS GPIO (see GPIO). |
| I2C_1_SCL | In/out | 1 | I2C bus serial
clock output. Second I2C. Can also be used as an MSS GPIO (see GPIO). |
| I2C_1_SDA | In/out | 1 | I2C bus serial
data input/output. Second I2C. Can also be used as an MSS GPIO (see GPIO). |
| Serial Peripheral Interface (SPI) Controllers | |||
| SPI_0_CLK | Out | 1 | Clock. First SPI. Can also be used as an MSS GPIO (see GPIO). |
| SPI_0_DI | In | 1 | Data input. First SPI. Can also be used as an MSS GPIO (see GPIO). |
| SPI_0_DO | Out | 1 | Data output. First SPI. Can also be used as an MSS GPIO (see GPIO). |
| SPI_0_SS | Out | 1 | Slave select (chip select). First SPI. Can also be used as an MSS GPIO (see GPIO). |
| SPI_1_CLK | Out | 1 | Clock. Second SPI. Can also be used as an MSS GPIO (see GPIO). |
| SPI_1_DI | In | 1 | Data input. Second SPI. Can also be used as an MSS GPIO (see GPIO). |
| SPI_1_DO | Out | 1 | Data output. Second SPI. Can also be used as an MSS GPIO (see GPIO). |
| SPI_1_SS | Out | 1 | Slave select (chip select). Second SPI. Can also be used as an MSS GPIO (see GPIO). |
| Universal Asynchronous Receiver/Transmitter (UART) Peripherals | |||
| UART_0_RXD | In | 1 | Receive data. First UART. Can also be used as an MSS GPIO (see GPIO). |
| UART_0_TXD | Out | 1 | Transmit data. First UART. Can also be used as an MSS GPIO (see GPIO). |
| UART_1_RXD | In | 1 | Receive data. Second UART. Can also be used as an MSS GPIO (see GPIO). |
| UART_1_TXD | Out | 1 | Transmit data. Second UART. Can also be used as an MSS GPIO (see GPIO). |
| Ethernet MAC | |||
| MAC_CLK | In | Rise | Receive clock. 50 MHz ± 50 ppm clock source received from RMII PHY. Can be left floating when unused. |
| MAC_CRSDV | In | High | Carrier sense/receive data valid for RMII
PHY Can also be used as an FPGA User IO (see IO). |
| MAC_MDC | Out | Rise | RMII management clock Can also be used as an FPGA User IO (see IO). |
| MAC_MDIO | In/Out | 1 | RMII management data input/output Can also be used as an FPGA User IO (see IO). |
| MAC_RXDx | In | 2 | Ethernet MAC receive data. Data recovered and
decoded by PHY. The RXD[0] signal is the least significant bit. Can also be used as an FPGA User I/O (see IO). |
| MAC_RXER | In | HIGH | Ethernet MAC receive error. If MACRX_ER is
asserted during reception, the frame is received and status of the frame is
updated with MACRX_ER. Can also be used as an FPGA user I/O (see IO). |
| MAC_TXDx | Out | 2 | Ethernet MAC transmit data. The TXD[0] signal
is the least significant bit. Can also be used as an FPGA user I/O (see IO). |
| MAC_TXEN | Out | HIGH | Ethernet MAC transmit enable. When asserted,
indicates valid data for the PHY on the TXD port. Can also be used as an FPGA User I/O (see IO). |