5.7 Microcontroller Subsystem (MSS)

NameTypePolarity/
Bus SizeDescription
External Memory Controller
EMC_ABxOut26External memory controller address bus

Can also be used as an FPGA user I/O (see IO).

EMC_BYTENxOutLOW/2External memory controller byte enable

Can also be used as an FPGA user I/O (see IO).

EMC_CLKOutRiseExternal memory controller clock

Can also be used as an FPGA user I/O (see IO).

EMC_CSx_NOutLOW/2External memory controller chip selects

Can also be used as an FPGA User IO (see IO ).

EMC_DBxIn/out16External memory controller data bus

Can also be used as an FPGA user I/O (see IO).

EMC_OENx_NOutLOW/2External memory controller output enables

Can also be used as an FPGA User IO (see IO).

EMC_RW_NOutLevelExternal memory controller read/write. Read = High, write = Low.

Can also be used as an FPGA user I/O (see IO).

Inter-Integrated Circuit (I2C) Peripherals
I2C_0_SCLIn/out1I2C bus serial clock output. First I2C.

Can also be used as an MSS GPIO (see GPIO).

I2C_0_SDAIn/out1I2C bus serial data input/output. First I2C.

Can also be used as an MSS GPIO (see GPIO).

I2C_1_SCLIn/out1I2C bus serial clock output. Second I2C.

Can also be used as an MSS GPIO (see GPIO).

I2C_1_SDAIn/out1I2C bus serial data input/output. Second I2C.

Can also be used as an MSS GPIO (see GPIO).

Serial Peripheral Interface (SPI) Controllers
SPI_0_CLKOut1Clock. First SPI.

Can also be used as an MSS GPIO (see GPIO).

SPI_0_DIIn1Data input. First SPI.

Can also be used as an MSS GPIO (see GPIO).

SPI_0_DOOut1Data output. First SPI.

Can also be used as an MSS GPIO (see GPIO).

SPI_0_SSOut1Slave select (chip select). First SPI.

Can also be used as an MSS GPIO (see GPIO).

SPI_1_CLKOut1Clock. Second SPI.

Can also be used as an MSS GPIO (see GPIO).

SPI_1_DIIn1Data input. Second SPI.

Can also be used as an MSS GPIO (see GPIO).

SPI_1_DOOut1Data output. Second SPI.

Can also be used as an MSS GPIO (see GPIO).

SPI_1_SSOut1Slave select (chip select). Second SPI.

Can also be used as an MSS GPIO (see GPIO).

Universal Asynchronous Receiver/Transmitter (UART) Peripherals
UART_0_RXDIn1Receive data. First UART.

Can also be used as an MSS GPIO (see GPIO).

UART_0_TXDOut1Transmit data. First UART.

Can also be used as an MSS GPIO (see GPIO).

UART_1_RXDIn1Receive data. Second UART.

Can also be used as an MSS GPIO (see GPIO).

UART_1_TXDOut1Transmit data. Second UART.

Can also be used as an MSS GPIO (see GPIO).

Ethernet MAC
MAC_CLKInRiseReceive clock. 50 MHz ± 50 ppm clock source received from RMII PHY.

Can be left floating when unused.

MAC_CRSDVInHighCarrier sense/receive data valid for RMII PHY

Can also be used as an FPGA User IO (see IO).

MAC_MDCOutRiseRMII management clock

Can also be used as an FPGA User IO (see IO).

MAC_MDIOIn/Out1RMII management data input/output

Can also be used as an FPGA User IO (see IO).

MAC_RXDxIn2Ethernet MAC receive data. Data recovered and decoded by PHY. The RXD[0] signal is the least significant bit.

Can also be used as an FPGA User I/O (see IO).

MAC_RXERInHIGHEthernet MAC receive error. If MACRX_ER is asserted during reception, the frame is received and status of the frame is updated with MACRX_ER.

Can also be used as an FPGA user I/O (see IO).

MAC_TXDxOut2Ethernet MAC transmit data. The TXD[0] signal is the least significant bit.

Can also be used as an FPGA user I/O (see IO).

MAC_TXENOutHIGHEthernet MAC transmit enable. When asserted, indicates valid data for the PHY on the TXD port.

Can also be used as an FPGA User I/O (see IO).