2.14 Serial Peripheral Interface (SPI) Characteristics
(Ask a Question)This section describes the DC and switching of the SPI interface. Unless otherwise noted, all output characteristics given for a 35 pF load on the pins and all sequential timing characteristics are related to SPI_x_CLK. For timing parameter definitions, see 2.14 Serial Peripheral Interface (SPI) Characteristics.
| Symbol | Description and Condition | A2F0603 | A2F500 | Unit |
|---|---|---|---|---|
| sp1 | SPI_x_CLK minimum period | |||
| SPI_x_CLK = PCLK/2 | 20 | 20 | ns | |
| SPI_x_CLK = PCLK/4 | 40 | 40 | ns | |
| SPI_x_CLK = PCLK/8 | 80 | 80 | ns | |
| SPI_x_CLK = PCLK/16 | 0.16 | 0.16 | µs | |
| SPI_x_CLK = PCLK/32 | 0.32 | 0.32 | µs | |
| SPI_x_CLK = PCLK/64 | 0.64 | 0.64 | µs | |
| SPI_x_CLK = PCLK/128 | 1.28 | 1.28 | µs | |
| SPI_x_CLK = PCLK/256 | 2.56 | 2.56 | µs | |
| sp2 | SPI_x_CLK minimum pulse width high | |||
| SPI_x_CLK = PCLK/2 | 10 | 10 | ns | |
| SPI_x_CLK = PCLK/4 | 20 | 20 | ns | |
| SPI_x_CLK = PCLK/8 | 40 | 40 | ns | |
| SPI_x_CLK = PCLK/16 | 0.08 | 0.08 | µs | |
| SPI_x_CLK = PCLK/32 | 0.16 | 0.16 | µs | |
| SPI_x_CLK = PCLK/64 | 0.32 | 0.32 | µs | |
| SPI_x_CLK = PCLK/128 | 0.64 | 0.64 | µs | |
| SPI_x_CLK = PCLK/256 | 1.28 | 1.28 | us | |
| sp3 | SPI_x_CLK minimum pulse width low | |||
| SPI_x_CLK = PCLK/2 | 10 | 10 | ns | |
| SPI_x_CLK = PCLK/4 | 20 | 20 | ns | |
| SPI_x_CLK = PCLK/8 | 40 | 40 | ns | |
| SPI_x_CLK = PCLK/16 | 0.08 | 0.08 | µs | |
| SPI_x_CLK = PCLK/32 | 0.16 | 0.16 | µs | |
| SPI_x_CLK = PCLK/64 | 0.32 | 0.32 | µs | |
| SPI_x_CLK = PCLK/128 | 0.64 | 0.64 | µs | |
| SPI_x_CLK = PCLK/256 | 1.28 | 1.28 | µs | |
| sp4 | SPI_x_CLK, SPI_x_DO, SPI_x_SS rise time (10%-90%) 1 | 4.7 | 4.7 | ns |
| sp5 | SPI_x_CLK, SPI_x_DO, SPI_x_SS fall time (10%-90%) 1 | 3.4 | 3.4 | ns |
| sp6 | Data from master (SPI_x_DO) setup time 2 | 1 | 1 | pclk cycles |
| sp7 | Data from master (SPI_x_DO) hold time 2 | 1 | 1 | pclk cycles |
| sp8 | SPI_x_DI setup time 1 | 1 | 1 | pclk cycles |
| sp9 | SPI_x_DI hold time 2 | 1 | 1 | pclk cycles |
Note:
- These values are provided for a load of 35 pF. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microchip website.
- For allowable pclk configurations, refer to the Serial Peripheral Interface Controller section in the SmartFusion Microcontroller Subsystem User’s Guide.
- Device A2F060 is discontinued.
