44.8.2 I2SC Mode Register

The I2SC_MR must be written when the I2SC is stopped. The proper sequence is to write to I2SC_MR, then write to I2SC_CR to enable the I2SC or to disable the I2SC before writing a new value to I2SC_MR.

Name:	I2SC_MR
Offset:	0x04
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	IWS	IMCKMODE	IMCKFS[5:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
			IMCKDIV[5:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
		TXSAME	TXDMA	TXMONO		RXLOOP	RXDMA	RXMONO
Access		R/W	R/W	R/W		R/W	R/W	R/W
Reset		0	0	0		0	0	0


Bit	7	6	5	4	3	2	1	0
				DATALENGTH[2:0]				MODE
Access				R/W	R/W	R/W		R/W
Reset				0	0	0		0

Bit 31 – IWS WS Slot Width

Refer to table Slot Length (I2S format).

Value	Description
0	WS slot is 32 bits wide for DATALENGTH = 18/20/24 bits.
1	WS slot is 24 bits wide for DATALENGTH = 18/20/24 bits.

Bit 30 – IMCKMODE Host Clock Mode

Warning: If MCK frequency is the same as CK, IMCKMODE must be cleared. Refer to section Serial Clock and Word Select Generation and table Slot Length.

Value	Description
0	No Host clock generated (Selected Clock drives CK output).
1	Host clock generated (internally generated clock is used as MCK output).

Bits 29:24 – IMCKFS[5:0] Host Clock to f_s Ratio

Host clock frequency is [2 x 16 × (IMCKFS + 1)] / (IMCKDIV + 1) times the sample rate, i.e., WS frequency.

Value	Name	Description
0	M2SF32	Sample frequency ratio set to 32
1	M2SF64	Sample frequency ratio set to 64
2	M2SF96	Sample frequency ratio set to 96
3	M2SF128	Sample frequency ratio set to 128
5	M2SF192	Sample frequency ratio set to 192
7	M2SF256	Sample frequency ratio set to 256
11	M2SF384	Sample frequency ratio set to 384
15	M2SF512	Sample frequency ratio set to 512
23	M2SF768	Sample frequency ratio set to 768
31	M2SF1024	Sample frequency ratio set to 1024
47	M2SF1536	Sample frequency ratio set to 1536
63	M2SF2048	Sample frequency ratio set to 2048

Bits 21:16 – IMCKDIV[5:0] Selected Clock to I2SC Host Clock Ratio

MCK Host clock output frequency is Selected Clock divided by (IMCKDIV + 1). Refer to the IMCKFS field description.

Note:

This field is write-only. Always read as ‘0’.
Do not write a ‘0’ to this field.

Bit 14 – TXSAME Transmit Data when Underrun

Value	Description
0	Zero sample transmitted when underrun.
1	Previous sample transmitted when underrun

Bit 13 – TXDMA Single or Multiple DMA Controller Channels for Transmitter DMA Controller Channels for Transmitter

Value	Description
0	The transmitter uses only one DMA Controller channel for all audio channels.
1	The transmitter uses one DMA Controller channel per audio channel.

Bit 12 – TXMONO Transmit Mono

Value	Description
0	Stereo
1	Mono, with left audio samples duplicated to right audio channel by the I2SC.

Bit 10 – RXLOOP Loopback Test Mode

Value	Description
0	Normal mode
1	DO output of I2SC is internally connected to DI input.

Bit 9 – RXDMA Single or Multiple DMA Controller Channels for Receiver

Value	Description
0	The receiver uses only one DMA Controller channel for all audio channels.
1	The receiver uses one DMA Controller channel per audio channel.

Bit 8 – RXMONO Receive Mono

Value	Description
0	Stereo
1	Mono, with left audio samples duplicated to right audio channel by the I2SC.

Bits 4:2 – DATALENGTH[2:0] Data Word Length

Value	Name	Description
0	32_BITS	Data length is set to 32 bits.
1	24_BITS	Data length is set to 24 bits.
2	20_BITS	Data length is set to 20 bits.
3	18_BITS	Data length is set to 18 bits.
4	16_BITS	Data length is set to 16 bits.
5	16_BITS_COMPACT	Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word.
6	8_BITS	Data length is set to 8 bits.
7	8_BITS_COMPACT	Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word.

Bit 0 – MODE Inter-IC Sound Controller Mode

Value	Name	Description
0	Client	CK and WS pin inputs used as bit clock and word select/frame synchronization.
1	Host	Bit clock and word select/frame synchronization generated by I2SC from MCK and output to CK and WS pins. Peripheral clock or GCLK is output as Host clock on MCK if I2SC_MR.IMCKMODE is set.