44.6.5 Serial Clock and Word Select Generation
The generation of clocks in the I2SC is described in Figure 44-3.
In Client mode, the serial clock and word select clock are driven by an external Host. CK and WS pins are inputs.
In Host mode, the user can configure the Host clock, serial clock, and word select clock through the MR. MAIN_CLK, CK, and WS pins are outputs and MAIN_CLK is used to derive the I2SC clocks.
In Host mode, if the peripheral clock frequency is higher than 96 MHz, the GCLK[PID] from PMC must be selected as I2SC input clock by writing a ‘1’ in the I2SCxCC bit of the CCFG_PCCR register. Refer to the section Bus Matrix (MATRIX) for additional information.
Audio codecs connected to the I2SC pins may require a Host clock (MAIN_CLK) signal with a frequency multiple of the audio sample frequency (fs), such as 256fs. When the I2SC is in Host mode, writing a ’1’ to MR.IMCKMODE outputs MAIN_CLK as Host clock to the MAIN_CLK pin, and divides MAIN_CLK to create the internal bit clock, output on the I2SC_CK pin. The clock division factor is defined by writing to MR.IMCKFS and MR.DATALENGTH, as described in the MR.IMCKFS field description.
The Host clock (MAIN_CLK) frequency is (2×16 × (IMCKFS + 1)) / (IMCKDIV + 1) times the sample frequency (fs), that is, WS frequency.
For example, If the sampling rate is 44.1 kHz with an I2S Host clock (MAIN_CLK) ratio of 256, the core frequency must be an integer multiple of 11.2896 MHz. Assuming an integer multiple of 4, the IMCKDIV field must be configured to 4; the field IMCKFS must then be set to 31.
The serial clock (CK) frequency is 2 × Slot Length times the sample frequency (fs), where Slot Length is defined in the following table.
| I2SC_MR.DATALENGTH | Word Length | Slot Length |
|---|---|---|
| 0 | 32 bits | 32 |
| 1 | 24 bits | 32 if MR.IWS = 0 24 if MR.IWS = 1 |
| 2 | 20 bits | |
| 3 | 18 bits | |
| 4 | 16 bits | 16 |
| 5 | 16 bits compact stereo | |
| 6 | 8 bits | 8 |
| 7 | 8 bits compact stereo |
If a Host clock output is not required, the MAIN_CLK clock is used as CK by clearing MR.IMCKMODE. Alternatively, if the frequency of the MAIN_CLK clock used is a multiple of the required CK frequency, the MAIN_CLK to CK divider can be used with the ratio defined by writing the MR.IMCKFS field.
The WS pin is used as word select as described in section “I2S Reception and Transmission Sequence”.