44.6.10 Interrupts

An I2SC interrupt request can be triggered whenever one or several of the following bits are set in SR: Receive Ready (RXRDY), Receive Overrun (RXOR), Transmit Ready (TXRDY) or Transmit Underrun (TXUR).

The interrupt request is generated if the corresponding bit in the Interrupt Mask Register (IMR) is set. Bits in IMR are set by writing a ’1’ to the corresponding bit in IER and cleared by writing a ’1’ to the corresponding bit in the Interrupt Disable Register (IDR). The interrupt request remains active until the corresponding bit in SR is cleared by writing a ’1’ to the corresponding bit in the Status Clear Register (SCR).

For debug purposes, interrupt requests can be simulated by writing a ’1’ to the corresponding bit in the Status Set Register (SSR).