40.8.5 SPI Status Register
| Name: | SPI_SR |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SPIENS | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| UNDES | TXEMPTY | NSSR | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OVRES | MODF | TDRE | RDRF | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 16 – SPIENS SPI Enable Status
| Value | Description |
|---|---|
| 0 | SPI is disabled. |
| 1 | SPI is enabled. |
Bit 10 – UNDES Underrun Error Status (Client mode only) (cleared on read)
| Value | Description |
|---|---|
| 0 | No underrun has been detected since the last read of SPI_SR. |
| 1 | A transfer starts whereas no data has been loaded in SPI_TDR. |
Bit 9 – TXEMPTY Transmission Registers Empty (cleared by writing SPI_TDR)
| Value | Description |
|---|---|
| 0 | As soon as data is written in SPI_TDR. |
| 1 | SPI_TDR and internal shift register are empty. If a transfer delay has been defined, TXEMPTY is set after the end of this delay. |
Bit 8 – NSSR NSS Rising (cleared on read)
| Value | Description |
|---|---|
| 0 | No rising edge detected on NSS pin since the last read of SPI_SR. |
| 1 | A rising edge occurred on NSS pin since the last read of SPI_SR. |
Bit 3 – OVRES Overrun Error Status (cleared on read)
An overrun occurs when SPI_RDR is loaded at least twice from the internal shift register since the last read of SPI_RDR.
| Value | Description |
|---|---|
| 0 | No overrun has been detected since the last read of SPI_SR. |
| 1 | An overrun has occurred since the last read of SPI_SR. |
Bit 2 – MODF Mode Fault Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No mode fault has been detected since the last read of SPI_SR. |
| 1 | A mode fault occurred since the last read of SPI_SR. |
Bit 1 – TDRE Transmit Data Register Empty (cleared by writing SPI_TDR)
TDRE is cleared when the SPI is disabled or at reset. Enabling the SPI sets the TDRE flag.
| Value | Description |
|---|---|
| 0 | Data has been written to SPI_TDR and not yet transferred to the internal shift register. |
| 1 | The last data written in SPI_TDR has been transferred to the internal shift register. |
Bit 0 – RDRF Receive Data Register Full (cleared by reading SPI_RDR)
| Value | Description |
|---|---|
| 0 | No data has been received since the last read of SPI_RDR. |
| 1 | Data has been received and the received data has been transferred from the internal shift register to SPI_RDR since the last read of SPI_RDR. |