12.1.2 Tightly Coupled Memory (TCM) Interface
The PIC32CZ CA70/MC70 devices embed TCM running at processor speed.
- ITCM is a single 64-bit interface, based at 0x0000 0000 (code region).
- DTCM is composed of dual 32-bit interfaces interleaved, based at 0x2000 0000 (data region).
ITCM and DTCM are enabled or disabled in the ITCMR and DTCMR registers in Arm SCB.
DTCM is enabled by default at reset. ITCM is disabled by default at reset.
There are four TCM configurations controlled by software. When enabled, ITCM is located at 0x0000 0000, overlapping ROM or Flash depending on the general-purpose NVM bit 1 (GPNVM). The configuration is done with GPNVM bits [8:7].
| ITCM | DTCM | SRAM | GPNVM Bits [8:7] |
|---|---|---|---|
| 0 | 0 | 512 | 0 |
| 32 | 32 | 448 | 1 |
| 64 | 64 | 384 | 2 |
| 128 | 128 | 256 | 3 |
Accesses made to TCM regions when the relevant TCM is disabled and accesses made to the Code and SRAM region above the TCM size limit are performed on the AHB matrix, that is, on internal Flash or on ROM depending on the remap GPNVM bit.
Accesses made to the SRAM above the size limit will not generate aborts.
The Memory Protection Unit (MPU) can to be used to protect these areas.