27.4.3.1 General Reset

A general reset occurs when a VDDIO POR is detected, a brown out or a voltage regulation loss is detected by the Supply Controller. The vddcore_nreset signal is asserted by the Supply Controller when a general reset occurs.

All the reset signals are released and RSTC_SR.RSTTYP reports a general reset. As the RSTC_MR is written to ‘0’, the NRST line rises two cycles after the vddcore_nreset, as ERSTL defaults at value 0x0.

The following figure illustrates how the general reset affects the reset signals.

Note: To ensure a correct watchdog reset of the system, the ERSTL field in the Reset Controller Mode Register must be set to a non-zero value ( RSTC_MR_ERSTL >=1).
Figure 27-3. General Reset Timing Diagram