39.4.3 PLL Specifications
Standard Operating Conditions
(unless otherwise stated) VDD > = 2.5V |
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Param No. | Sym. | Characteristic | Min. | Typ. † | Max. | Units | Conditions |
PLL01 | FPLLIN | PLL Input Frequency Range | 4 | — | 16 | MHz | |
PLL02 | FPLLOUT | PLL Output Frequency Range | 16 | — | 64 | MHz | (Note 1) |
PLL03* | FPLLST | PLL Lock Time from Start-up | — | 200 | — | μs | |
PLL04* | FPLLJIT | PLL Output Frequency Stability (Jitter) | -0.25 | — | 0.25 | % | |
* - These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:
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