5.6.2 OSCCON2

Oscillator Control Register 2
Note:
  1. The POR value is the value present when user code execution begins.
  2. The Reset value (q/q) is the same as the NOSC/NDIV bits.
  3. EXTOSC configured by the CONFIG1[FEXTOSC] bits.
  4. HFINTOSC frequency is set with the HFFRQ bits.
  5. EXTOSC must meet the PLL specifications.
Name: OSCCON2
Address: 0xED4

Bit 76543210 
  COSC[2:0]CDIV[3:0] 
Access RRRRRRR 
Reset qqqqqqq 

Bits 6:4 – COSC[2:0]  Current Oscillator Source Select bits (read-only)(1,2)

Indicates the current source oscillator and PLL combination as shown in the following table.

Table 5-5. COSC Bit Settings
COSC/NOSCClock Source
111 EXTOSC(3)
110 HFINTOSC(4)
101 LFINTOSC
100 SOSC
011 Reserved
010 EXTOSC + 4x PLL(5)
001 Reserved
000 Reserved

Bits 3:0 – CDIV[3:0]  Current Divider Select bits (read-only)(1,2)

Indicates the current postscaler division ratio as shown in the follwing table.

Table 5-4. CDIV Bit Settings
CDIV/NDIV Clock Divider
1111-1010 Reserved
1001 512
1000 256
0111 128
0110 64
0101 32
0100 16
0011 8
0010 4
0001 2
0000 1
The POR value is the value present when user code execution begins.The Reset value (q/q) is the same as the NOSC New Oscillator Source Request bits(1,2,3) /NDIV New Divider Selection Request bits(2,3) bits.EXTOSC configured by the CONFIG1[FEXTOSC] bits. HFINTOSC frequency is set with the HFFRQHFINTOSC Frequency Selection bits bits. EXTOSC must meet the PLL specifications.