5.6.1 OSCCON1
Note:
- The default value (f/f) is determined by the CONFIG1[RSTOSC] Configuration bits. See Table 5-2.
- If NOSC is written with a reserved value (Table 5-3), the operation is ignored and NOSC is not written.
- When CONFIG1[CSWEN] =
0
, this register is read-only and cannot be changed from the POR value. - EXTOSC must meet the PLL specifications.
- EXTOSC configured by CONFIG1[FEXTOSC].
- HFINTOSC frequency is set with the HFFRQ bits.
- EXTOSC must meet the PLL specifications.
Name: | OSCCON1 |
Address: | 0xED3 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
NOSC[2:0] | NDIV[3:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | f | f | f | f | f | f | f |
Bits 6:4 – NOSC[2:0] New Oscillator Source Request bits(1,2,3)
The setting requests a source oscillator and PLL combination per Table 5-3.
CONFIG1[RSTOSC] | SFR Reset Values (fff ffff) | Initial FOSC Frequency | ||
---|---|---|---|---|
NOSC/COSC | NDIV/CDIV | OSCFRQ | ||
111 |
111 |
0000 |
4 MHz | EXTOSC per FEXTOSC |
110 |
110 |
0010 |
FOSC = 1 MHz (4 MHz/4) | |
101 |
101 |
0000 |
LFINTOSC | |
100 |
100 |
0000 |
SOSC | |
011 |
Reserved | |||
010 |
010 |
0000 |
4 MHz | EXTOSC + 4xPLL(4) |
001 |
Reserved | |||
000 |
110 |
0000 |
64 MHz | FOSC = 64 MHz |
NOSC[2:0] | Clock Source |
---|---|
111 |
EXTOSC(5) |
110 |
HFINTOSC(6) |
101 |
LFINTOSC |
100 |
SOSC |
011 |
Reserved |
010 |
EXTOSC + 4x PLL(7) |
001 |
Reserved |
000 |
Reserved |
Bits 3:0 – NDIV[3:0] New Divider Selection Request bits(2,3)
The setting determines the new postscaler division ratio per Table 5-1.
NDIV[3:0] | Clock Divider |
---|---|
1111-1010 |
Reserved |
1001 |
512 |
1000 |
256 |
0111 |
128 |
0110 |
64 |
0101 |
32 |
0100 |
16 |
0011 |
8 |
0010 |
4 |
0001 |
2 |
0000 |
1 |