26.2 CLC Interrupts

An interrupt will be generated upon a change in the output value of the CLCx when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in each CLC for this purpose.

The CLCxIF bit of the associated PIR register will be set when either edge detector is triggered and its associated enable bit is set. The INTP enables rising edge interrupts and the INTN bit enables falling edge interrupts.

To fully enable the interrupt, set the following bits:
  • CLCxIE bit of the respective PIE register
  • INTP bit (for a rising edge detection)
  • INTN bit (for a falling edge detection)
  • If priority interrupts are not used
    • Clear the IPEN bit of the INTCON register
    • Set the GIE bit of the INTCON register
    • Set the PEIE bit of the INTCON register
  • If the CLC is a high-priority interrupt
    • Set the IPEN bit of the INTCON register
    • Set the CLCxIP bit of the respective IPR register
    • Set the GIEH bit of the INTCON register
  • If the CLC is a low-priority interrupt
    • Set the IPEN bit of the INTCON register
    • Clear the CLCxIP bit of the respective IPR register
    • Set the GIEL bit of the INTCON register

The CLCxIF bit of the respective PIR register, must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence.