26.8.1 CLCxCON

Configurable Logic Cell Control Register
Name: CLCxCON
Address: 0xE27,0xE31,0xE3B,0xE45,0xE4F,0xE59,0xE63,0xE6D

Bit 76543210 
 EN OUTINTPINTNMODE[2:0] 
Access R/WROR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 7 – EN

CLC Enable bit
ValueDescription
1 Configurable logic cell is enabled and mixing signals
0 Configurable logic cell is disabled and has logic zero output

Bit 5 – OUT

Logic cell output data, after LCPOL. Sampled from CLCxOUT

Bit 4 – INTP

Configurable Logic Cell Positive Edge Going Interrupt Enable bit
ValueDescription
1 CLCxIF will be set when a rising edge occurs on CLCxOUT
0 Rising edges on CLCxOUT have no effect on CLCxIF

Bit 3 – INTN

Configurable Logic Cell Negative Edge Going Interrupt Enable bit
ValueDescription
1 CLCxIF will be set when a falling edge occurs on CLCxOUT
0 Falling edges on CLCxOUT have no effect on CLCxIF

Bits 2:0 – MODE[2:0]

Configurable Logic Cell Functional Mode Selection bits
ValueDescription
111 Cell is 1-input transparent latch with Set and Reset
110 Cell is J-K flip-flop with Reset
101 Cell is 2-input D flip-flop with Reset
100 Cell is 1-input D flip-flop with Set and Reset
011 Cell is S-R latch
010 Cell is 4-input AND
001 Cell is OR-XOR
000 Cell is AND-OR