25.2.1 Half-Bridge Mode

In Half-Bridge mode, two output signals are generated as true and inverted versions of the input as illustrated in Figure 25-1. A non-overlap (dead-band) time is inserted between the two outputs to prevent shoot-through current in various power supply applications. Dead-band control is described in 25.7 Dead-Band Control. The output steering feature cannot be used in this mode. A basic block diagram of this mode is shown in Figure 25-2.

The unused outputs CWGxC and CWGxD drive similar signals, with polarity independently controlled by the POLC and POLD bits, respectively.

Figure 25-1. CWG Half-Bridge Mode Operation

Note: CWGx_rising_src = CCP1_out, CWGx_falling_src = ~CCP1_out
Figure 25-2. Simplified CWG Block Diagram (Half-Bridge Mode, MODE[2:0] = 100)