3.4.6 Power Supply System

To avoid on board self-generated disturbances within the PLC signal band (35 to 472 kHz), a linear (non-switched topology) AC/DC power supply schematic based on a power transformer plus full-wave rectifier is used to generate the unregulated DC voltage “VDC” and two high frequency buck converters to get the power levels required. An F1 fuse and VR1 varistor are used as protective devices in the equipment input, and an F2 fuse protects the transformer output against overcurrent situations.

Figure 3-12. Linear AC/DC Power Supply Design

The mains rms input voltage range of PL360MB is selectable by means of jumpers on connector J2:

  • 230VACrms ±10% mains voltage range: A jumper must be placed in the middle pins of connector J2, as shown in the following figure.
    Figure 3-13. J2 Jumper Configuration for 230VACrms ±10%
  • 115VACrms ±10% mains voltage range: Two jumpers must be placed in connector J2. See following figure.
    Figure 3-14. J2 Jumper Configuration for 115VACrms ±10%
Figure 3-15. VDC Voltage Design

The “VDC” voltage rail is used as input power of a high switching frequency buck converter to generate the regulated DC voltage “VDD”, which is used to power the class-D amplifier of the PLC coupling circuit. The output level of the buck converter is selectable between 12V and 16V by means of jumper J16. Refer to sections PLCOUP007 Board and PLCOUP006 Board to see how the jumper J16 must be configured depending on the PLC coupling board being used.

CAUTION: Be careful with the VDD voltage selected, because the PLC coupling driver board PLCOUPxxx could be damaged. Please check the features of these boards to select the operation voltage.

Take into account that PLCOUP006 and PLCOUP007 boards use 12 volts.

VDD buck converter has a shutdown circuit enable which is controlled by the “3V3 EN” signal. This signal is an output pin of SAM4CMS16C, “SHDN”. This feature lets PL360MB boards enter in a low power mode. When PL360MB is supplied “3V3 EN” signal is in low value voltage as to not disable the VDD buck converter. The DC Jack connector (J15) can be used to supply an external board to VDD volts (400 mA at 12 V).

Figure 3-16. VDD Buck Converter Design

A second buck converter with switching frequency above the highest PLC frequency band is also used to generate a regulated 3.3V voltage rail required by PL360 and the MCU. The current consumption from 3.3V voltage rail can be measured connecting an ammeter in the placeholder of jumper J17.

Figure 3-17. 3.3V Buck Converter Design

Other 1.2V voltage levels are generated by the embedded LDOs on SAM4CMS16C. For more detailed information about these LDOs, refer to SAM4CM Series Datasheet.

There is a LED and a test point on each voltage rail to check whether all power supplies are operating properly.

Tip: If choosing a different SMPS in your custom design, it is important to analyze its potential interference on the PLC frequency band.