12.10.13 Peripheral Interrupt Request Register 3
Note: Interrupt flag
bits are set when an Interrupt condition occurs, regardless of the state of its
corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the
appropriate interrupt flag bits are cleared before enabling an interrupt.
| Name: | PIR3 |
| Offset: | 0x008F |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PWM2IF | PWM2PIF | PWM1IF | PWM1PIF | ||||||
| Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 3 – PWM2IF PWM2 Parameter Interrupt Flag
| Value | Description |
|---|---|
| 1 | PWM2 Parameter interrupt has occurred (must be cleared in software) |
| 0 | PWM2 Parameter interrupt event has not occurred |
Bit 2 – PWM2PIF PWM2 Period Interrupt Flag
| Value | Description |
|---|---|
| 1 | PWM2 Period interrupt has occurred (must be cleared in software) |
| 0 | PWM2 Period interrupt event has not occurred |
Bit 1 – PWM1IF PWM1 Parameter Interrupt Flag
| Value | Description |
|---|---|
| 1 | PWM1 Parameter interrupt has occurred (must be cleared in software) |
| 0 | PWM1 Parameter interrupt event has not occurred |
Bit 0 – PWM1PIF PWM1 Period Interrupt Flag
| Value | Description |
|---|---|
| 1 | PWM1 Period interrupt has occurred (must be cleared in software) |
| 0 | PWM1 Period interrupt event has not occurred |