12.10.17 Peripheral Interrupt Request Register 7
Note: Interrupt flag
bits are set when an Interrupt condition occurs, regardless of the state of its
corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the
appropriate interrupt flag bits are cleared before enabling an interrupt.
| Name: | PIR7 |
| Offset: | 0x0093 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLB1IF3 | CLB1IF2 | CLB1IF1 | CLB1IF0 | ||||||
| Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 3 – CLB1IF3 CLB1 Interrupt Flag 3
| Value | Description |
|---|---|
| 1 | CLB1 interrupt 3 occurred (must be cleared in software) |
| 0 | CLB1 interrupt 3 has not occurred |
Bit 2 – CLB1IF2 CLB1 Interrupt Flag 2
| Value | Description |
|---|---|
| 1 | CLB1 interrupt 2 occurred (must be cleared in software) |
| 0 | CLB1 interrupt 2 has not occurred |
Bit 1 – CLB1IF1 CLB2 Interrupt Flag 1
| Value | Description |
|---|---|
| 1 | CLB1 interrupt 1 has occurred (must be cleared in software) |
| 0 | CLB1 interrupt 1 event has not occurred |
Bit 0 – CLB1IF0 CLB1 Interrupt Flag 0
| Value | Description |
|---|---|
| 1 | CLB1 interrupt 0 has occurred (must be cleared in software) |
| 0 | CLB1 interrupt 0 event has not occurred |