29.4.2 Programmable Edge Detectors

The output of each of the 16 input selection latches are fed into programmable edge detectors. The edge detectors may be positive edge-triggered, negative edge-triggered, or bypassed completely.

If the edge detectors are bypassed, the input signal is fed directly to the CLB without synchronization as shown in Figure 29-4when bit 0 of the CLB Input Synchronizer selector is 0. If the bit is 1, then bit 1 selects whether the rising or falling edge of the input triggers the edge detector. In either case, the signal is then synchronized to CLBCLK. As with the edge detector, the synchronizer may also be bypassed as shown in the illustrations.

Important: If any of the BLEs are programmed to use its output flop, care must be taken so that the unsynchronized input does not cause the BLE flop to go into metastability.

Figure 29-4. Edge Detector Operation when CLB Input Synchronizer[2:0] = '00X'

Figure 29-5. Edge Detector Operation when CLB Input Synchronizer[2:0] = '010'

Figure 29-6. Edge Detector Operation when CLB Input Synchronizer[2:0] = '011'

Figure 29-7. Edge Detector Operation when CLB Input Synchronizer[2:0] = '10X'

Figure 29-8. Edge Detector Operation when CLB Input Synchronizer[2:0] = '110'

Figure 29-9. Edge Detector Operation when CLB Input Synchronizer[2:0] = '111'