42.4.16 SPI Mode Requirements

Table 42-2. SPI Mode
Standard Operating Conditions (unless otherwise stated)
Param No.Sym.CharacteristicMin.Typ. †Max.UnitsConditions
SP70*

TSSL2SCH,

TSSL2SCL

SDO to SCK↓ or SCK↑ input2.25*TCY——ns
SP70A*0——ns
SP71*TSCHSCK output high time TCY + 20—0.5*TSCK + 12 ns
SP72*TSCLSCK output low timeTCY + 20—0.5*TSCK + 12 ns
SP73*

TDIV2SCH,

TDIV2SCL

Setup time of SDI data input to SCK edge85——ns
SP74*

TSCH2DIL,

TSCL2DIL

Hold time of SDI data input to SCK edge0——ns
SP74A*Hold time of SDI data input to final SCK0.5*TSCKnsCKE = 0,

SMP = 1

SP75*TDORSDO data output rise time—1025nsCL = 50 pF
SP76*TDOFSDO data output fall time—1025nsCL = 50 pF
SP78*TSCRSCK output rise time—1025nsCL = 50 pF
SP79*TSCFSCK output fall time—1025nsCL = 50 pF
SP80*

TSCH2DOV,

TSCL2DOV

SDO data output valid after SCK edge———nsCL = 50 pF
SP81*

TDOV2SCH,

TDOV2SCL

SDO data output valid to first SCK edge1*TCY——ns

CL = 50 pF

CKE = 1

SP82*TSSL2DOVSDO data output valid after SS↓ edge——50nsCL = 20 pF
SP83*

TSCH2SSH,

TSCL2SSH

SS ↑ after last SCK edge1.5*TCY + 40——ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:
  1. The SMP bit in the SSPxSTAT register must be set and the slew rate control must be disabled on the clock and data pins (clear the corresponding bits in SLRCONx register) for SPI to operate over 4 MHz.
Figure 42-15. SPI Host Mode Timing (CKE = 0, SMP = 0)
Note: Refer to Figure 42-3 for load conditions.
Figure 42-16. SPI Host Mode Timing (CKE = 1, SMP = 1)
Note: Refer to Figure 42-3 for load conditions.
Figure 42-17. SPI Client Mode Timing (CKE = 0)
Note: Refer to Figure 42-3 for load conditions.
Figure 42-18. SPI Client Mode Timing (CKE = 1)
Note: Refer to Figure 42-3 for load conditions.