42.4.20 Configurable Logic Block (CLB) Characteristics


Standard Operating Conditions (unless otherwise stated)
Param No.	Sym.	Characteristic	Min.	Typ. †	Max.	Units	Conditions
CLB01*	T_CONFIG	CLB Configuration loading time	—	206	—	Instruction Cycles (T_CY)	MD = `'b01`,Burst Mode
CLB02*	I_{DD_SYNC_8}	Synchronous 50% BLE Design - 8 MHz Input Signal⁽³⁾	—	85	—	μA/MHz (CLB CLK)	V_DD = 1.8V
CLB02A*			—	155	—	μA/MHz (CLB CLK)	V_DD = 3.0V
CLB02B*			—	330	—	μA/MHz (CLB CLK)	V_DD = 5.5V
CLB03*	I_{DD_SYNC_0}	Synchronous 50% BLE Design - 0 MHz Input Signal⁽³⁾	—	45	—	μA/MHz (CLB CLK)	V_DD = 1.8V
CLB03A*			—	95	—	μA/MHz (CLB CLK)	V_DD = 3.0V
CLB03B*			—	205	—	μA/MHz (CLB CLK)	V_DD = 5.5V
CLB04*	I_{DD_ASYNC}	Asynchronous 50% BLE Design⁽³⁾	—	40	—	μA/MHz	V_DD = 1.8V
CLB04A*			—	90	—	μA/MHz	V_DD = 3.0V
CLB04B*			—	200	—	μA/MHz	V_DD = 5.5V
* These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: For CLB application analysis tools and information, please refer to logic.microchip.com/clbsynthesizer/ When calculating CLB timing, I/O pad timing should also be considered. Please refer to I/O and CLKOUT Timing Specifications for I/O timing specifications. 50% BLE utilization, no input synchronization, -40°C to 125°C.