2.10.3 RAM Configurations

The AX architecture allows the read side and write side of RAMs to be organized independently, allowing for bus conversion. For example, the write side can be set to 256x18 and the read side to 512x9.

Both the write width and read width for the RAM blocks can be specified independently and changed dynamically with the WW (write width) and RW (read width) pins. The D x W different configurations are: 128 x 36, 256 x 18, 512 x 9, 1k x 4, 2k x 2, and 4k x 1. The allowable RW and WW values are shown in the following table.

Table 2-91. Allowable RW and WW Values
RW(2:0)WW(2:0)D x W
0000004k x 1
0010012k x 2
0100101k x 4
011011512 x 9
100100256 x 18
101101128 x 36
11x11xreserved

When widths of one, two, and four are selected, the ninth bit is unused. For example, when writing nine-bit values and reading four-bit values, only the first four bits and the second four bits of each nine-bit value are addressable for read operations. The ninth bit is not accessible. Conversely, when writing four-bit values and reading nine-bit values, the ninth bit of a read operation will be undefined.

Note that the RAM blocks employ little-endian byte order for read and write operations.

The following table lists the RAM signals and their descriptions.

Table 2-92. RAM Signal Description
SignalDirectionDescription
WCLKInputWrite clock (can be active on either edge)
WA[J:0]InputWrite address bus.The value J is dependent on the RAM configuration and the number of cascaded memory blocks. The valid range for J is from 6 to15.
WD[M-1:0]InputWrite data bus. The value M is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36.
RCLKInputRead clock (can be active on either edge)
RA[K:0]InputRead address bus. The value K is dependent on the RAM configuration and the number of cascaded memory blocks. The valid range for K is from 6 to 15.
RD[N-1:0]OutputRead data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36.
RENInputRead enable. When this signal is valid on the active edge of the clock, data at location RA will be driven onto RD.
WENInputWrite enable. When this signal is valid on the active edge of the clock, WD data will be written at location WA.
RW[2:0]InputWidth of the read operation dataword
WW[2:0]InputWidth of the write operation dataword
PipeInputSets the pipe option to be on or off