2.10.4 Modes of Operation

There are two read modes and one write mode:

• Read Nonpipelined (synchronous—one clock edge)
• Read Pipelined (synchronous—two clock edges)
• Write (synchronous—one clock edge)

In the standard read mode, new data is driven onto the RD bus in the clock cycle immediately following RA and REN valid. The read address is registered on the read-port active-clock edge and data appears at read-data after the RAM access time. Setting the PIPE to OFF enables this mode.

The pipelined mode incurs an additional clock delay from address to data, but enables operation at a much higher frequency. The read-address is registered on the read-port active-clock edge, and the read data is registered and appears at RD after the second read clock edge. Setting the PIPE to On enables this mode.

On the write active-clock edge, the write data are written into the SRAM at the write address when Wen is high. The setup time of the write address, write enables, and write data are minimal with respect to the write clock.

Write and read transfers are described with timing requirements beginning in the Timing Characteristics.