2.10.12 Building RAM and FIFO Modules

RAM and FIFO modules can be generated and included in a design in two different ways:

Using the SmartGen Core Generator where the user defines the depth and width of the FIFO/RAM, and then instantiates this block into the design (for more information, see the SmartGen, FlashROM, Analog System Builder, and Flash Memory System Builder User’s Guide).
The alternative is to instantiate the RAM/FIFO blocks manually, using inverters for polarity control and tying all unused data bits to ground.

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