2.3.11.2 Timing Characteristics

The following table lists the timing characteristics of 3.3V PCI.

Table 2-39. 3.3V PCI I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2 Speed		–1 Speed		Std Speed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
3.3V PCI Output Module Timing
t_DP	Input buffer	—	1.57	—	1.79	—	2.10	ns
t_PY	Output buffer	—	1.91	—	2.18	—	2.56	ns
t_ENZL	Enable to pad delay through the output buffer—Z to low	—	1.61	—	1.62	—	1.63	ns
t_ENZH	Enable to pad delay through the output buffer—Z to high	—	1.45	—	1.47	—	1.47	ns
t_ENLZ	Enable to pad delay through the output buffer—low to Z	—	2.55	—	2.90	—	3.41	ns
t_ENHZ	Enable to pad delay through the output buffer—high to Z	—	3.52	—	4.01	—	4.72	ns
t_IOCLKQ	Sequential Clock-to-Q for the I/O input register	—	0.67	—	0.77	—	0.90	ns
t_IOCLKY	Clock-to-output Y for the I/O output register and the I/O enable register	—	0.67	—	0.77	—	0.90	ns
t_SUD	Data input set-up	—	0.23	—	0.27	—	0.31	ns
t_SUE	Enable input set-up	—	0.26	—	0.30	—	0.35	ns
t_HD	Data input hold	—	0.00	—	0.00	—	0.00	ns
t_HE	Enable input hold	—	0.00	—	0.00	—	0.00	ns
t_CPWHL	Clock pulse width high to low	0.39	—	0.39		0.39	—	ns
t_CPWLH	Clock pulse width low to high	0.39	—	0.39		0.39	—	ns
t_WASYN	Asynchronous pulse width	0.37	—	0.37		0.37	—	ns
t_REASYN	Asynchronous recovery time	—	0.13	—	0.15	—	0.17	ns
t_HASYN	Asynchronous removal time	—	0.00	—	0.00	—	0.00	ns
t_CLR	Asynchronous Clear-to-Q	—	0.23	—	0.27	—	0.31	—
t_PRESET	Asynchronous Preset-to-Q	—	0.23	—	0.27	—	0.31	ns

The following table lists the timing characteristics of 3.3V PCI-X.

Table 2-40. 3.3V PCI-X I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
—		–2 Speed		–1 Speed		Std Speed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
3.3V PCI-X Output Module Timing
t_DP	Input buffer	—	1.57	—	1.79	—	2.10	ns
t_PY	Output buffer	—	2.10	—	2.40	—	2.82	ns
t_ENZL	Enable to pad delay through the output buffer—Z to low	—	1.61	—	1.62	—	1.63	ns
t_ENZH	Enable to pad delay through the output buffer—Z to high	—	1.59	—	1.60	—	1.61	ns
t_ENLZ	Enable to pad delay through the output buffer—low to Z	—	2.65	—	3.02	—	3.55	ns
t_ENHZ	Enable to pad delay through the output buffer—high to Z	—	3.11	—	3.55	—	4.17	ns
t_IOCLKQ	Sequential Clock-to-Q for the I/O input register	—	0.67	—	0.77	—	0.90	ns
t_IOCLKY	Clock-to-output Y for the I/O output register and the I/O enable register	—	0.67	—	0.77	—	0.90	ns
t_SUD	Data input set-up	—	0.23	—	0.27	—	0.31	ns
t_SUE	Enable input set-up	—	0.26	—	0.30	—	0.35	ns
t_HD	Data input hold	—	0.00	—	0.00	—	0.00	ns
t_HE	Enable input hold	—	0.00	—	0.00	—	0.00	ns
t_CPWHL	Clock pulse width high to low	0.39	—	0.39	—	0.39	—	ns
t_CPWLH	Clock pulse width low to high	0.39	—	0.39	—	0.39	—	ns
t_WASYN	Asynchronous pulse width	0.37	—	0.37	—	0.37	—	ns
t_REASYN	Asynchronous recovery time	—	0.13	—	0.15	—	0.17	ns
t_HASYN	Asynchronous removal time	—	0.00	—	0.00	—	0.00	ns
t_CLR	Asynchronous Clear-to-Q	—	0.23	—	0.27	—	0.31	ns
t_PRESET	Asynchronous Preset-to-Q	—	0.23	—	0.27	—	0.31	ns