2.3.9.2 Timing Characteristics

The following table lists the timing characteristics of 1.8V LVCMOS.

Table 2-33. 1.8V LVCMOS I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 1.7V, T_J = 70 °C
Parameter	Description	–2 Speed		–1 Speed		Std Speed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
LVCMOS18 Output Module Timing
t_DP	Input buffer	—	3.26	—	3.71	—	4.37	ns
t_PY	Output buffer	—	4.55	—	5.18	—	6.09	ns
t_ENZL	Enable to pad delay through the output buffer—Z to low	—	2.82	—	2.83	—	2.84	ns
t_ENZH	Enable to pad delay through the output buffer—Z to high	—	3.43	—	3.45	—	3.46	ns
t_ENLZ	Enable to pad delay through the output buffer—low to Z	—	6.01	—	6.85	—	8.05	ns
t_ENHZ	Enable to pad delay through the output buffer—high to Z	—	6.73	—	7.67	—	9.01	ns
t_IOCLKQ	Sequential Clock-to-Q for the I/O input register	—	0.67	—	0.77	—	0.90	ns
t_IOCLKY	Clock-to-output Y for the I/O output register and the I/O enable register	—	0.67	—	0.77	—	0.90	ns
t_SUD	Data input set-up	—	0.23	—	0.27	—	0.31	ns
t_SUE	Enable input set-up	—	0.26	—	0.30	—	0.35	ns
t_HD	Data input hold	—	0.00	—	0.00	—	0.00	ns
t_HE	Enable input hold	—	0.00	—	0.00	—	0.00	ns
t_CPWHL	Clock pulse width high to low	0.39	—	0.39	—	0.39	—	ns
t_CPWLH	Clock pulse width low to high	0.39	—	0.39	—	0.39	—	ns
t_WASYN	Asynchronous pulse width	0.37	—	0.37	—	0.37	—	ns
t_REASYN	Asynchronous recovery time	—	0.13	—	0.15	—	0.17	ns
t_HASYN	Asynchronous removal time	—	0.00	—	0.00	—	0.00	ns
t_CLR	Asynchronous Clear-to-Q	—	0.23	—	0.27	—	0.31	ns
t_PRESET	Asynchronous Preset-to-Q	—	0.23	—	0.27	—	0.31	ns