2.3.7.2 Timing Characteristics

The following table lists the timing characterisitics of 3.3V LVTTL.

Table 2-27. 3.3V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2 Speed		–1 Speed		Std Speed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
LVTTL Output Drive Strength = 1 (8 mA)/Low Slew Rate
t_DP	Input buffer	—	1.68	—	1.92	—	2.26	ns
t_PY	Output buffer	—	14.28	—	16.27	—	19.13	ns
t_ENZL	Enable to pad delay through the output buffer—Z to low	—	15.25	—	17.37	—	20.42	ns
t_ENZH	Enable to pad delay through the output buffer—Z to high	—	14.26	—	16.24	—	19.09	ns
t_ENLZ	Enable to pad delay through the output buffer—low to Z	—	1.56	—	1.57	—	1.58	ns
t_ENHZ	Enable to pad delay through the output buffer—high to Z	—	1.95	—	1.96	—	1.97	ns
t_IOCLKQ	Sequential Clock-to-Q for the I/O input register	—	0.67	—	0.77	—	0.90	ns
t_IOCLKY	Clock-to-output Y for the I/O output register and the I/O enable register	—	0.67	—	0.77	—	0.90	ns
t_SUD	Data input set-up	—	0.23	—	0.27	—	0.31	ns
t_SUE	Enable input set-up	—	0.26	—	0.30	—	0.35	ns
t_HD	Data input hold	—	0.00	—	0.00	—	0.00	ns
t_HE	Enable input hold	—	0.00	—	0.00	—	0.00	ns
t_CPWHL	Clock pulse width high to low	0.39	—	0.39	—	0.39	—	ns
t_CPWLH	Clock pulse width low to high	0.39	—	0.39	—	039	—	ns
t_WASYN	Asynchronous pulse width	0.37	—	0.37	—	0.37	—	ns
t_REASYN	Asynchronous recovery time	—	0.13	—	0.15	—	0.17	ns
t_HASYN	Asynchronous removal time	—	0.00	—	0.00	—	0.00	ns
t_CLR	Asynchronous Clear-to-Q	—	0.23	—	0.27	—	0.31	ns
t_PRESET	Asynchronous Preset-to-Q	—	0.23	—	0.27	—	0.31	ns
t_DP	Input buffer	—	1.68	—	1.92	—	2.26	ns
t_PY	Output buffer	—	12.14	—	13.83	—	16.26	ns
t_ENZL	Enable to pad delay through the output buffer—Z to low	—	12.43	—	14.16	—	16.65	ns
t_ENZH	Enable to pad delay through the output buffer—Z to high	—	12.17	—	13.86	—	16.30	ns
t_ENLZ	Enable to pad delay through the output buffer—low to Z	—	1.73	—	1.74	—	1.75	ns
t_ENHZ	Enable to pad delay through the output buffer—high to Z	—	2.22	—	2.23	—	2.24	ns
t_IOCLKQ	Sequential Clock-to-Q for the I/O input register	—	0.67	—	0.77	—	0.90	ns
t_IOCLKY	Clock-to-Output Y for the I/O output register and the I/O enable register	—	0.67	—	0.77	—	0.90	ns
t_SUD	Data input set-up	—	0.23	—	0.27	—	0.31	ns
t_SUE	Enable input set-up	—	0.26	—	0.30	—	0.35	ns
t_HD	Data input hold	—	0.00	—	0.00	—	0.00	ns
t_HE	Enable input hold	—	0.00	—	0.00	—	0.00	ns
t_CPWHL	Clock pulse width high to low	0.39	—	0.39	—	0.38	—	ns
t_CPWLH	Clock pulse width low to high	0.39	—	0.39	—	0.39	—	ns
t_WASYN	Asynchronous pulse width	0.37	—	0.37	—	0.37	—	ns
t_REASYN	Asynchronous recovery time	—	0.13	—	0.15	—	0.17	ns
t_HASYN	Asynchronous removal time	—	0.00	—	0.00	—	0.00	ns
t_CLR	Asynchronous Clear-to-Q	—	0.23	—	0.27	—	0.31	ns
t_PRESET	Asynchronous Preset-to-Q	—	0.23	—	0.27	—	0.31	ns
t_DP	Input buffer	—	1.68	—	1.92	—	2.26	ns
t_PY	Output buffer	—	11.03	—	12.56	—	14.77	ns
t_ENZL	Enable to pad delay through the output buffer—Z to low	—	11.42	—	13.01	—	15.29	ns
t_ENZH	Enable to pad delay through the output buffer—Z to high	—	11.04	—	12.58	—	14.79	ns
t_ENLZ	Enable to pad delay through the output buffer—low to Z	—	1.86	—	1.88	—	1.88	ns
t_ENHZ	Enable to pad delay through the output buffer—high to Z	—	2.50	—	2.51	—	2.52	ns
t_IOCLKQ	Sequential Clock-to-Q for the I/O input register	—	0.67	—	0.77	—	0.90	ns
t_IOCLKY	Clock-to-Output Y for the I/O output register and the I/O enable register	—	0.67	—	0.77	—	0.90	ns
t_SUD	Data input set-up	—	0.23	—	0.27	—	0.31	ns
t_SUE	Enable input set-up	—	0.26	—	0.30	—	0.35	ns
t_HD	Data input hold	—	0.00	—	0.00	—	0.00	ns
t_HE	Enable input hold	—	0.00	—	0.00	—	0.00	ns
t_CPWHL	Clock pulse width high to low	0.39	—	0.39	—	0.39	—	ns
t_CPWLH	Clock pulse width low to high	0.39	—	0.39	—	0.39	—	ns
t_WASYN	Asynchronous pulse width	0.37	—	0.37	—	0.37	—	ns
t_REASYN	Asynchronous recovery time	—	0.13	—	0.15	—	0.17	ns
t_HASYN	Asynchronous removal time	—	0.00	—	0.00	—	0.00	ns
t_CLR	Asynchronous Clear-to-Q	—	0.23	—	0.27	—	0.31	ns
t_PRESET	Asynchronous Preset-to-Q	—	0.23	—	0.27	—	0.31	ns
t_DP	Input buffer	—	1.68	—	1.92	—	2.26	ns
t_PY	Output buffer	—	10.45	—	11.90	—	13.99	ns
t_ENZL	Enable to pad delay through the output buffer—Z to low	—	10.61	—	12.08	—	14.21	ns
t_ENZH	Enable to pad delay through the output buffer—Z to high	—	10.47	—	11.93	—	14.02	ns
t_ENLZ	Enable to pad delay through the output buffer—low to Z	—	1.92	—	1.94	—	1.94	ns
t_ENHZ	Enable to pad delay through the output buffer—high to Z	—	2.57	—	2.58	—	2.59	ns
t_IOCLKQ	Sequential Clock-to-Q for the I/O input register	—	0.67	—	0.77	—	0.90	ns
t_IOCLKY	Clock-to-Output Y for the I/O output register and the I/O enable register	—	0.67	—	0.77	—	0.90	ns
t_SUD	Data input set-up	—	0.23	—	0.27	—	0.31	ns
t_SUE	Enable input set-up	—	0.26	—	0.30	—	0.35	ns
t_HD	Data input hold	—	0.00	—	0.00	—	0.00	ns
t_HE	Enable input hold	—	0.00	—	0.00	—	0.00	ns
t_CPWHL	Clock pulse width high to low	0.39	—	0.39	—	0.39	—	ns
t_CPWLH	Clock pulse width low to high	0.39	—	0.39	—	0.39	—	ns
t_WASYN	Asynchronous pulse width	0.37	—	0.37	—	0.37	—	ns
t_REASYN	Asynchronous recovery time	—	0.13	—	0.15	—	0.17	ns
t_HASYN	Asynchronous removal time	—	0.00	—	0.00	—	0.00	ns
t_CLR	Asynchronous Clear-to-Q	—	0.23	—	0.27	—	0.31	ns
t_PRESET	Asynchronous Preset-to-Q	—	0.23	—	0.27	—	0.31	ns
t_DP	Input buffer	—	1.68	—	1.92	—	2.26	ns
t_PY	Output buffer	—	4.23	—	4.81	—	5.66	ns
t_ENZL	Enable to pad delay through the output buffer—Z to low	—	4.64	—	5.28	—	6.21	ns
t_ENZH	Enable to pad delay through the output buffer—Z to high	—	4.23	—	4.81	—	5.66	ns
t_ENLZ	Enable to pad delay through the output buffer—low to Z	—	1.89	—	1.91	—	1.91	ns
t_ENHZ	Enable to pad delay through the output buffer—high to Z	—	2.01	—	2.02	—	2.03	ns
t_IOCLKQ	Sequential Clock-to-Q for the I/O input register	—	0.67	—	0.77	—	0.90	ns
t_IOCLKY	Clock-to-output Y for the I/O output register and the I/O enable register	—	0.67	—	0.77	—	0.90	ns
t_SUD	Data input set-up	—	0.23	—	0.27	—	0.31	ns
t_SUE	Enable input set-up	—	0.26	—	0.30	—	0.35	ns
t_HD	Data input hold	—	0.00	—	0.00	—	0.00	ns
t_HE	Enable input hold	—	0.00	—	0.00	—	0.00	ns
t_CPWHL	Clock pulse width high to low	0.39	—	0.39	—	0.39	—	ns
t_CPWLH	Clock pulse width low to high	0.39	—	0.39	—	0.39	—	ns
t_WASYN	Asynchronous pulse width	0.37	—	0.37	—	0.37	—	ns
t_REASYN	Asynchronous recovery time	—	0.13	—	0.15	—	0.17	ns
t_HASYN	Asynchronous removal time	—	0.00	—	0.00	—	0.00	ns
t_CLR	Asynchronous Clear-to-Q	—	0.23	—	0.27	—	0.31	ns
t_PRESET	Asynchronous Preset-to-Q	—	0.23	—	0.27	—	0.31	ns
t_DP	Input buffer	—	1.68	—	1.92	—	2.26	ns
t_PY	Output buffer	—	3.30	—	3.76	—	4.42	ns
t_ENZL	Enable to pad delay through the output buffer—Z to low	—	3.74	—	4.26	—	5.00	ns
t_ENZH	Enable to pad delay through the output buffer—Z to high	—	3.06	—	3.49	—	4.10	ns
t_ENLZ	Enable to pad delay through the output buffer—low to Z	—	1.89	—	1.91	—	1.91	ns
t_ENHZ	Enable to pad delay through the output buffer—high to Z	—	2.29	—	2.30	—	2.31	ns
t_IOCLKQ	Sequential Clock-to-Q for the I/O input register	—	0.67	—	0.77	—	0.90	ns
t_IOCLKY	Clock-to-output Y for the I/O output register and the I/O enable register	—	0.67	—	0.77	—	0.90	ns
t_SUD	Data input set-up	—	0.23	—	0.27	—	0.31	ns
t_SUE	Enable input set-up	—	0.26	—	0.30	—	0.35	ns
t_HD	Data input hold	—	0.00	—	0.00	—	0.00	ns
t_HE	Enable input hold	—	0.00	—	0.00	—	0.00	ns
t_CPWHL	Clock pulse width high to low	0.39	—	0.39	—	0.39	—	ns
t_CPWLH	Clock pulse width low to high	0.39	—	0.39	—	0.39	—	ns
t_WASYN	Asynchronous pulse width	0.37	—	0.37	—	0.37	—	ns
t_REASYN	Asynchronous recovery time	—	0.13	—	0.15	—	0.17	ns
t_HASYN	Asynchronous removal time	—	0.00	—	0.00	—	0.00	ns
t_CLR	Asynchronous Clear-to-Q	—	0.23	—	0.27	—	0.31	ns
t_PRESET	Asynchronous Preset-to-Q	—	0.23	—	0.27	—	0.31	ns
t_DP	Input buffer	—	1.68	—	1.92	—	2.26	ns
t_PY	Output buffer	—	3.12	—	3.56	—	4.18	ns
t_ENZL	Enable to pad delay through the output buffer—Z to low	—	3.54	—	4.04	—	4.75	ns
t_ENZH	Enable to pad delay through the output buffer—Z to high	—	2.78	—	3.17	—	3.72	ns
t_ENLZ	Enable to pad delay through the output buffer—low to Z	—	1.91	—	1.93	—	1.93	ns
t_ENHZ	Enable to pad delay through the output buffer—high to Z	—	2.58	—	2.59	—	2.60	ns
t_IOCLKQ	Sequential Clock-to-Q for the I/O input register	—	0.67	—	0.77	—	0.90	ns
t_IOCLKY	Clock-to-output Y for the I/O output register and the I/O enable register	—	0.67	—	0.77	—	0.90	ns
t_SUD	Data input set-up	—	0.23	—	0.27	—	0.31	ns
t_SUE	Enable input set-up	—	0.26	—	0.30	—	0.35	ns
t_HD	Data input hold	—	0.00	—	0.00	—	0.00	ns
t_HE	Enable input hold	—	0.00	—	0.00	—	0.00	ns
t_CPWHL	Clock pulse width high to low	0.39	—	0.39	—	0.39	—	ns
t_CPWLH	Clock pulse width low to high	0.39	—	0.39	—	0.39	—	ns
t_WASYN	Asynchronous pulse width	0.37	—	0.37	—	0.37	—	ns
t_REASYN	Asynchronous recovery time	—	0.13	—	0.15	—	0.17	ns
t_HASYN	Asynchronous removal time	—	0.00	—	0.00	—	0.00	ns
t_CLR	Asynchronous Clear-to-Q	—	0.23	—	0.27	—	0.31	ns
t_PRESET	Asynchronous Preset-to-Q	—	0.23	—	0.27	—	0.31	ns
t_DP	Input buffer	—	1.68	—	1.92	—	2.26	ns
t_PY	Output buffer	—	2.99	—	3.41	—	4.01	ns
t_ENZL	Enable to pad delay through the output buffer—Z to low	—	2.49	—	2.51	—	2.51	ns
t_ENZH	Enable to pad delay through the output buffer—Z to high	—	2.59	—	2.95	—	3.46	ns
t_ENLZ	Enable to pad delay through the output buffer—low to Z	—	1.91	—	1.93	—	1.93	ns
t_ENHZ	Enable to pad delay through the output buffer—high to Z	—	3.56	—	4.06	—	4.77	ns
t_IOCLKQ	Sequential Clock-to-Q for the I/O input register	—	0.67	—	0.77	—	0.90	ns
t_IOCLKY	Clock-to-output Y for the I/O output register and the I/O enable register	—	0.67	—	0.77	—	0.90	ns
t_SUD	Data input set-up	—	0.23	—	0.27	—	0.31	ns
t_SUE	Enable input set-up	—	0.26	—	0.30	—	0.35	ns
t_HD	Data input hold	—	0.00	—	0.00	—	0.00	ns
t_HE	Enable input hold	—	0.00	—	0.00	—	0.00	ns
t_CPWHL	Clock pulse width high to low	0.39	—	0.39	—	0.39	—	ns
t_CPWLH	Clock pulse width low to high	0.39	—	0.39	—	0.39	—	ns
t_WASYN	Asynchronous pulse width	0.37	—	0.37	—	0.37	—	ns
t_REASYN	Asynchronous recovery time	—	0.13	—	0.15	—	0.17	ns
t_HASYN	Asynchronous removal time	—	0.00	—	0.00	—	0.00	ns
t_CLR	Asynchronous Clear-to-Q	—	0.23	—	0.27	—	0.31	ns
t_PRESET	Asynchronous Preset-to-Q	—	0.23	—	0.27	—	0.31	ns