9.6.1 Overview

Most peripherals are connected to two clock domains:
  • The peripheral digital bus interface, which is connected to the APB or AHB bus and is clocked by the corresponding synchronous clock in the Main Clock domain
  • The peripheral core clock, which is connected to the peripheral Generic Clock (GCLK_PERIPH[n])

Communication between these clock domains must be synchronized. This mechanism is implemented in hardware, so the synchronization process takes place even if the peripheral Generic Clock is running from the same clock source and at the same frequency as the synchronous bus clock.

All registers in the bus interface are accessible without synchronization.

All registers in a peripheral are synchronized when written. Some registers are also synchronized when read.

Register descriptions will include the properties “Read-Synchronized” and/or “Write-Synchronized” if a register is synchronized.

As shown in the figure below, each register that requires synchronization has its own synchronization mechanism and its individual synchronization status bit in the peripheral Synchronization Busy (SYNCBUSY) register.

Note: For registers that require both read and write synchronization, the corresponding SYNCBUSY bit is shared.
Figure 9-3. Register Synchronization Overview