9.6.6 Software Reset Write Synchronization

Writing a ‘1’ to the Software Reset (SWRST) bit in the CTRLA register will trigger write synchronization and set the Software Reset Synchronization Busy (SWRST) bit of the Synchronization Busy (SYNCBUSY) register.

When writing a ‘1’ to the CTRLA.SWRST bit, it will immediately read as ‘1’. Both CTRLA.SWRST and SYNCBUSY.SWRST will be cleared by hardware when the peripheral has been reset. Writing a ‘0’ to the CTRLA.SWRST bit has no effect. The Synchronization Ready interrupt (if available) cannot be used for Software Reset write synchronization.