9.6.5 Write-Synchronization for CTRLA.ENABLE

Writing a ‘1’ to the Enable bit in the Control A register (CTRLA.ENABLE) of a peripheral will trigger write-synchronization and set the Enable Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE).

The updated value of the CTRLA.ENABLE bit will be available immediately after it is written.

The SYNCBUSY.ENABLE bit will be cleared by hardware when the operation is complete.

The Synchronization Ready interrupt (if available) cannot be used to enable write synchronization.

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