9.6.7 Synchronization Delay

Synchronization will delay the duration of read and write access duration by a delay D, as shown in the equation below:

5 \times P_{GCLK} + 2 \times P_{APB} < D < 6 \times P_{GCLK} + 3 \times P_{APB}

Where:

P_GCLK is the period of the generic clock
P_APB is the period of the peripheral bus clock

A normal peripheral bus register access duration is $2 \times P_{APB}$ .

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