9.6.2 General Write Synchronization
Write Synchronization is triggered by writing to a register in the Peripheral Clock domain. The respective bit in the Synchronization Busy (SYNCBUSY) register will be set when the write synchronization starts and cleared when the write synchronization is complete. Refer to the Synchronization Delay section for details on the synchronization delay.
As long as write synchronization is ongoing for a register, any write attempts to that register will be discarded, and an error will be reported.
The following is an example of how this synchronization works. REGA and REGB are 8-bit core registers, and REGC is a 16-bit core register.
Write-synchronization example
| Offset | Register |
|---|---|
| 0x00 | REGA |
| 0x01 | REGB |
| 0x02 | REGC |
| 0x03 |
Synchronization is performed separately for each register, so multiple registers can be synchronized in parallel. Users can write to REGA (8-bit access) and then immediately write to REGB (8-bit access) without error.
Users can write to REGC (16-bit access) without affecting REGA or REGB. However, if a user writes to to REGC in two consecutive 8-bit accesses without waiting for synchronization, the second write attempt will be discarded and an error will be generated.
A 32-bit write access to offset 0x00 will write to all three registers. Note that REGA, REGB and REGC can be updated at different times because of independent write synchronization.