13.4.3.1.1 Clock Failure Detection

The CFD is disabled at reset. The CFD does not monitor the XOSC32K clock when:

The XOSC32K oscillator is disabled (the ENABLE bit in the XOSC32KCTRL register is ‘0’).
The XOSC32K oscillator is not running (the XOSC32KRDY bit in the STATUS register is ‘0’), that is, when not in sleep and the ONDEMAND bit in the XOSC32KCTRL register (XOSC32KCTRL.ONDEMAND) is ‘1’ and no peripherals are requesting the XOSC32K oscillator.

Enabling the CFD will automatically request the safe (monitor) clock, such as OSC32K.

CFD operation is started by setting the CFD Enable bit in the CFD Control register (CFDCTRL.CFDEN) to ‘1’. After starting or restarting XOSC32K, the CFD does not detect failure until the start-up time has elapsed. The start-up time is configured by the CSUT bit field in the XOSC32KCTRL register. Once the XOSC32K start-up time is elapsed, the XOSC32K clock is constantly monitored.

Note: The ready timer for XOSC32K uses a CSUT-controlled count of XOSC32K cycles before the XOSC32KRDY signal is asserted. Since the CFD does not detect a failure until the start-up time has elapsed, a total XOSC32K failure (i.e., the oscillator never starts) will not be detected by the CFD. The application must handle this case by waiting for the XOSC32KRDY after enabling XOSC32K to know that the oscillator has indeed started. Enabling the CFD detector alone, without waiting for the XOSC32KRDY, is not sufficient.

During a period of four safe clocks (monitor period), the CFD watches for a clock activity from the XOSC32K. There must be at least one rising and one falling XOSC32K clock edge during four safe clock periods to meet non-failure conditions. If no or insufficient activity is detected, the failure status is asserted: the Clock Failure Detector status bit (CLKFAIL) in the STATUS register and the Clock Failure Detector interrupt flag bit (CLKFAIL) in the INTFLAG register are both set to ‘1’. If the XOSC32K Clock Failure Detected bit (CLKFAIL) in the INTENSET register is set, an interrupt is generated. If the Event Output enable bit (CFDEO) in the Event Control register (EVCTRL) is set, an output event is generated.

After a clock failure is detected, monitoring of the XOSC32K clock continues, and the Clock Failure Detector status bit (CLKFAIL) in the STATUS register reflects the current XOSC32K activity. If the CFD is disabled (CFDEN bit in the CFDCTRL register is ‘0’), XOSC32K must be disabled (ENABLE bit in the XOSC32KCTRL register is ‘0’) before re-enabling the CFD. Not following this guideline can lead to a false clock failure detection. When the XOSC32K Clock Failure Detector is enabled (CFDEN bit in the CFDCTRL register is ‘1’) and a failure is detected (CLKFAIL bit in the STATUS register is ‘1’), the XOSC32KRDY bit in the STATUS register is not cleared. When checking the XOSC32K ready status, the state of the XOSC32K clock failure status (CLKFAIL bit in the STATUS register) must be checked before the XOSC32KRDY bit, and the XOSC32KRDY status bit should be disregarded if the XOSC32K clock failure status is set (CLKFAIL bit in the STATUS register is ‘1’).