13.4.3.1.2 Clock Switch

When a clock failure is detected, the XOSC32K clock is replaced by the safe clock in order to maintain an active clock during the XOSC32K clock failure. The safe clock source is the OSC32K oscillator clock. Both 32.768 kHz and 1.024 kHz outputs of the XOSC32K are replaced by the respective 32.768 kHz and 1.024 kHz OSC32K outputs. The safe clock source can be scaled down by a configurable prescaler to ensure that the safe clock frequency does not exceed the operating conditions selected by the application. When the XOSC32K clock is switched to the safe clock, the XOSC32K Clock Switch bit (CLKSW) in the STATUS register is set by hardware.

When the CFD has switched to the safe clock, XOSC32K is not disabled. If desired, the application must take the necessary actions to disable the oscillator. The application must also take the necessary actions to configure the system clocks to continue normal operations. If the application can recover XOSC32K, it can switch back to the XOSC32K clock by setting the Switch Back Enable bit (SWBACK) in the CFDCTRL register to '1' . Once the XOSC32K clock is switched back, the SWBACK bit in the CFDCTRL register is cleared by hardware.