22.6.8 Status

Note: This register is read- and write-synchronized: SYNCBUSY.STATUS must be checked to ensure the STATUS register synchronization is complete.

Name:	STATUS
Offset:	0x0B
Reset:	0x01
Property:	Read-Synchronized, Write-Synchronized


Bit	7	6	5	4	3	2	1	0
			CCBUFV1	CCBUFV0	PERBUFV		SLAVE	STOP
Access			R/W	R/W	R/W		R	R
Reset			0	0	0		0	1

Bits 4, 5 – CCBUFVn Channel n Compare or Capture Buffer Valid

For a compare channel n, the bit n is set when a new value is written to the corresponding CCBUF[n] register.

The bit n is cleared by writing a ‘1’ to it when CTRLB.LUPD is set, or it is cleared automatically by the hardware on UPDATE condition.

For a capture channel n, the bit n is set when a valid capture value is stored in the CCBUF[n] register. The bit n is cleared automatically when the CC[n] register is read.

Bit 3 – PERBUFV Period Buffer Valid

This bit is set when a new value is written to the PERBUF register. The bit is cleared by writing ‘1’ to the corresponding location when CTRLB.LUPD is set, or automatically cleared by the hardware on UPDATE condition.

Bit 1 – SLAVE Client Status Flag

This bit is only available in 32-bit mode on the client (odd-numbered TCn). The bit is set when the associated host (even-numbered TCn) is set to run in 32-bit mode.

Bit 0 – STOP Stop Status Flag

This bit is set when the TC is disabled, on a Stop command, or on an overflow/underflow condition when the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is ‘1’.

Value	Description
0	The counter is running
1	The counter is stopped