22.6.6 Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Any changes made to this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x09
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
   MC1MC0  ERROVF 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 4, 5 – MCn Match or Capture Channel n Interrupt Enable

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to MCn will set the corresponding Match or Capture Channel n Interrupt Enable bit, which enables the Match or Capture Channel n interrupt.

ValueDescription
0 The Match or Capture Channel n interrupt is disabled
1 The Match or Capture Channel n interrupt is enabled

Bit 1 – ERR Error Interrupt Enable

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.

ValueDescription
0 The Error interrupt is disabled
1 The Error interrupt is enabled

Bit 0 – OVF Overflow Interrupt Enable

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt request.

ValueDescription
0 The Overflow interrupt is disabled
1 The Overflow interrupt is enabled