22.6.15 Channel n Compare/Capture
Note: This register is write-synchronized:
SYNCBUSY.CC[n] must be checked to ensure the CC[n] register synchronization is complete.
| Name: | CC[n] |
| Offset: | 0x1C + n*0x01 [n=0..1] |
| Reset: | 0x00 |
| Property: | Write-Synchronized |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CC[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |