26.6.4 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
| Name: | INTENSET |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Property: | Local Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERROR | READY | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – ERROR Error Interrupt Enable
Writing a '0' to this bit has no
effect.
Writing a '1' to this bit sets the Error
interrupt enable.
| Value | Description |
|---|---|
| 0 | The Error interrupt is disabled |
| 1 | The Error interrupt is enabled |
Bit 0 – READY NVM Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit sets the NVM Ready interrupt
enable.
| Value | Description |
|---|---|
| 0 | The NVM Ready interrupt is disabled |
| 1 | The NVM Ready interrupt is enabled |