15.1 Device-Specific Information

Table 15-1. PWM Summary Table
PWM Module Instances	Number of PWM Events	Combinatorial PWM Logic	Outputs per Instance	Peripheral Bus Speed	Clock Generator
8	6	6	2	Normal (1:2 of CPU clock)	Clock Generator 5

Table 15-2. Auxiliary PWM Summary Table
PWM Module Instances	Number of PWM Events	Combinatorial PWM Logic	Outputs per Instance	Peripheral Bus Speed	Clock Generator
4	4	4	2	Normal (1:2 of CPU clock)	Clock Generator 5

Table 15-3. MCLKSEL PWM Master Clock Selection
Value	Description
`1`	Clock Generator 5
`0`	Normal (1:2 of CPU clock)

Table 15-4. PCI Source Selection (PSS)
PSS bits in PGxyPCI2 registers	Description
31 (0x80000000)	CLC1 output
30 (0x40000000)	Comparator 3 output
29 (0x20000000)	Comparator 2 output
28 (0x10000000)	Comparator 1 output
27 (0x8000000)	APWM event B
26 (0x4000000)	APWM event A
25 (0x2000000)	PWM event C
24 (0x1000000)	PWM event B
23 (0x800000)	PWM event A
22 (0x400000)	RPn Input PCI22R
21 (0x200000)	RPn Input PCI21R
20 (0x100000)	RPn Input PCI20R
19 (0x80000)	RPn Input PCI19R
18 (0x40000)	RPn Input PCI18R
17 (0x20000)	RPn Input PCI17R
16 (0x10000)	RPn Input PCI16R
15 (0x8000)	RPn Input PCI15R
14 (0x4000)	RPn Input PCI14R
13 (0x2000)	RPn Input PCI13R
12 (0x1000)	RPn Input PCI12R
11 (0x800)	RPn Input PCI11R
10 (0x400)	RPn Input PCI10R
9 (0x200)	RPn Input PCI9R
8 (0x100)	RPn Input PCI8R
7-4 (0x80, 0x40, 0x20, 0x10)	Reserved
3 (0x8)	Internally connected to Combo Trigger B
2 (0x4)	Internally connected to Combo Trigger A
1 (0x2)	Internally connected to the output of PWMPCI[2:0] bits in PGxEVT1 registers
0	Tied to ‘0’
Note: Each numbered entry in the first column corresponds to the position of the bit in the PGxPCI2 registers. The number in the parenthesis is the hexadecimal bit mask.