27.5 CLC Application Example

Figure 27-4 depicts the configuration of CLC to generate Frequency Shift Key (FSK) modulation on a UART signal using CLC.

Figure 27-4. CLC Configuration for FSK Generation
Note: Inverter operation shown in Figure 27-4 is done using the CLC register bits.
The peripherals required for this application are:
  • CLC1
  • UART data as modulator signal
  • Peripheral clock (carrier signal of higher frequency) to modulate logic ‘1’
  • LPRC (carrier signal of lower frequency) to modulate logic ‘0’
Note: UART, system clock and LPRC are used as examples for the modulator signal and carrier signal, respectively. However, it is possible to choose other sources as modulator and carrier signals.

The following is the application code for FSK modulation of the UART data.

FSK Modulation of UART Data

// Select input sources for CLC1
CLC1SELbits.DS1 = 0;     // Standard (1:2 CPU Clock) - high frequency carrier
CLC1SELbits.DS2 = 0b101; // Virtual Pin 6 Output (RPV6) - UART TX modulation signal
CLC1SELbits.DS3 = 0;     // BFRC/256 - low frequency carrier

// Configure Gates of CLC1 for FSK (AND-OR mode)
// Gate 1 inputs (active when UART TX = 1, passes high freq carrier)
CLC1GLSbits.G1D1T = 1;   // G1: DS1 non-inverted (high freq carrier)
CLC1GLSbits.G2D2T = 1;   // G2: DS2 non-inverted (UART TX)

// Gate 2 inputs (active when UART TX = 0, passes low freq carrier)
CLC1GLSbits.G3D2N = 1;   // G3: DS2 inverted (NOT UART TX)
CLC1GLSbits.G4D3T = 1;   // G4: DS3 non-inverted (low freq carrier)

// Configure CLC1 mode and output
CLC1CONbits.LCOE = 1;    // Enable CLC output on IO pin
CLC1CONbits.MODE = 0;    // Select AND-OR logic function

// Map UART1 TX to Virtual Pin 6 (RP135/RPV6) for CLC input
_RP135R = _RPOUT_U1TX;
    
// Enable CLC1
CLC1CONbits.ON = 1;