29.4.1 Programmable Input Edge Detectors

The output of each of the 16 input selection latches is fed into programmable edge detectors. The CLB Input Synchronizer[2:0] register, which is configured using the Microchip CLB Synthesizer, determines whether the edge detectors are positive edge-triggered, negative edge-triggered, or bypassed completely. The CLB Input Synchronizer[2:0] register also determines whether the output of the edge detectors are synchronous or asynchronous to the CLB clock.

Figure 29-3. Edge Detector Block Diagram

Bit 0 of the CLB Input Synchronizer register determines the polarity of the CLB Input Selection signal to the edge detector circuit. When Bit 0 is clear, the edge detector will trigger off of the original (non-inverted) input signal polarity. When Bit 0 is set, the edge detector will trigger off of the inverted input signal polarity.

Bit 1 of the CLB Input Synchronizer register determines whether the CLB Input Selection signal is the output the edge detector circuit or bypasses the edge detector circuit completely. When Bit 1 is clear, the edge detector circuit is bypassed. When Bit 1 is set, the Input Selection signal is the output of the edge detector circuit, which is triggered based on the edge selected by Bit 0.

Important: When Bit 1 of the CLB Input Synchronizer register is set, the edge detector circuitry is reset by module hardware automatically.

Bit 2 of the CLB Input Synchronizer register determines whether the output of the edge detector (or the bypassed CLB input signal) is syncronized to the CLB clock or fed into the BLE input selection mux asynchronously. When Bit 2 is clear, the input signal is asynchronous to the CLB clock. When Bit 2 is set, the input signal is synchronized to the CLB clock, typically after three CLB clock cycles.

The illustrations below show examples of different CLB Input Synchronizer register configurations.

Important: If any of the BLEs are programmed to use its output flop, care must be taken so that the unsynchronized input does not cause the BLE flop to go into metastability.

Figure 29-4. Edge Detector Operation when CLB Input Synchronizer[2:0] = '00X'

In Figure 29-4, the non-inverted CLB Input Selection signal bypasses the edge detector and is used as an asynchronous BLE Input Selection.

Figure 29-5. Edge Detector Operation when CLB Input Synchronizer[2:0] = '010'

In Figure 29-5, the non-inverted CLB Input Selection signal passes through the edge detector and is used as an asynchronous BLE Input Selection. The edge detector circuit is reset by module hardware.

Figure 29-6. Edge Detector Operation when CLB Input Synchronizer[2:0] = '011'

In Figure 29-6, the inverted CLB Input Selection signal passes through the edge detector and is used as an asynchronous BLE Input Selection. The edge detector circuit is reset by module hardware.

Figure 29-7. Edge Detector Operation when CLB Input Synchronizer[2:0] = '10X'

In Figure 29-7, the non-inverted CLB Input Selection signal bypasses the edge detector and is synchronized to the CLB clock.

Figure 29-8. Edge Detector Operation when CLB Input Synchronizer[2:0] = '110'

In Figure 29-8, the non-inverted CLB Input Selection signal passes through the edge detector and is synchronized on the rising edge of the CLB clock. The edge detector circuit is reset by module hardware.

Figure 29-9. Edge Detector Operation when CLB Input Synchronizer[2:0] = '111'

In Figure 29-9, the inverted CLB Input Selection signal passes through the edge detector and is synchronized on the falling edge of the CLB clock. The edge detector circuit is reset by module hardware.