27.11.2 MATRIX Client Configuration Register x
This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.
| Register MATRIX_ | Matrix 0 | Matrix 1 | Matrix 2 | Matrix 3 |
|---|---|---|---|---|
| SCFG0 | 0x000001FF | 0x000001FF | 0x001201FF | 0x000101FF |
| SCFG1 | 0x000001FF | 0x000001FF | 0x001201FF | 0x000101FF |
| SCFG2 | 0x000001FF | 0x000001FF | 0x001201FF | 0x000001FF |
| SCFG3 | 0x000001FF | 0x000001FF | 0x000A01FF | 0x000001FF |
| SCFG4 | 0x000001FF | 0x000001FF | 0x000D01FF | 0x000001FF |
| SCFG5 | 0x000001FF | 0x000001FF | 0x001201FF | 0x000001FF |
| SCFG6 | 0x000001FF | 0x000001FF | 0x000101FF | 0x000001FF |
| SCFG7 | 0x000001FF | 0x000001FF | 0x000A01FF | 0x000001FF |
| SCFG8 | 0x000001FF | 0x000001FF | 0x000D01FF | 0x000001FF |
| SCFG9 | 0x000001FF | 0x000001FF | 0x001201FF | 0x000001FF |
| SCFG10 | 0x000001FF | 0x000001FF | 0x000101FF | 0x00001FF |
| SCFG11 | 0x000001FF | 0x000001FF | 0x000001FF | 0x000001FF |
| SCFG12 | 0x000001FF | 0x000001FF | 0x000001FF | 0x000001FF |
| SCFG13 | 0x000001FF | 0x000001FF | 0x000001FF | 0x000001FF |
| SCFG14 | 0x000001FF | 0x000001FF | 0x000001FF | 0x000001FF |
| SCFG15 | 0x000001FF | 0x000001FF | 0x000001FF | 0x000001FF |
| Name: | MATRIX_SCFGx |
| Offset: | 0x40 + x*0x04 [x=0..15] |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FIXED_DEFMSTR[3:0] | DEFMSTR_TYPE[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | |||||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SLOT_CYCLE[8] | |||||||||
| Access | R/W | ||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SLOT_CYCLE[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | |||||||||
Bits 21:18 – FIXED_DEFMSTR[3:0] Fixed Default Host
This is the number of the Default Host for this client. Only used if DEFMSTR_TYPE is 2. Specifying the number of a host which is not connected to the selected client is equivalent to setting DEFMSTR_TYPE to 0.
Bits 17:16 – DEFMSTR_TYPE[1:0] Default Host Type
| Value | Name | Description |
|---|---|---|
| 0 | NONE | No Default Host—At the end of the current client access, if no other host request is pending, the client is disconnected from all hosts. This results in a one clock cycle latency for the first access of a burst transfer or for a single access. |
| 1 | LAST | Last Default Host—At the end of the current client access, if no other host request is pending, the client stays connected to the last host having accessed it. This results in not having one clock cycle latency when the last host tries to access the client again. |
| 2 | FIXED | Fixed Default Host—At the end of the current client access, if no other host request is pending, the client connects to the fixed host the number that has been written in the FIXED_DEFMSTR field. This results in not having one clock cycle latency when the fixed host tries to access the client again. |
Bits 8:0 – SLOT_CYCLE[8:0] Maximum Bus Grant Duration for Hosts
When SLOT_CYCLE system bus clock cycles have elapsed since the last arbitration, a new arbitration takes place to let another host access this client. If another host is requesting the client bus, then the current host burst is broken.
If SLOT_CYCLE = 0, the Slot Cycle Limit feature is disabled and bursts always complete unless broken according to the ULBT.
This limit has been placed in order to enforce arbitration so as to meet potential latency constraints of hosts waiting for client access.
This limit must not be too small. Unreasonably small values break every burst and the MATRIX arbitrates without performing any data transfer. The default maximum value is usually an optimal conservative choice.
In most cases, this feature is not needed and should be disabled for power saving.
See Slot Cycle Limit Arbitration for details.