27.11.16 MATRIX Protected Peripheral Select x Registers [x=1..3]
This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.
| Name: | MATRIX_PPSELRx |
| Offset: | 0x02C0 + (x-1)*0x04 [x=1..3] |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| USERP31 | USERP30 | USERP29 | USERP28 | USERP27 | USERP26 | USERP25 | USERP24 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| USERP23 | USERP22 | USERP21 | USERP20 | USERP19 | USERP18 | USERP17 | USERP16 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| USERP15 | USERP14 | USERP13 | USERP12 | USERP11 | USERP10 | USERP9 | USERP8 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| USERP7 | USERP6 | USERP5 | USERP4 | USERP3 | USERP2 | USERP1 | USERP0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – USERPy User PSELy Peripheral
| Value | Description |
|---|---|
| 0 |
The PSELx[y] APB Peripheral address space is configured as Privileged access. |
| 1 |
The PSELx[y] APB Peripheral address space is configured as User access. |