47.7.4 MCSPI Client Mode

When operating in Client mode, the MCSPI processes data bits on the clock provided on the MCSPI clock pin (SPCK).

The MCSPI waits until NSS goes active before receiving the serial clock from an external host. When NSS falls, the clock is validated and the data is loaded in MCSPI_RDR depending on the configuration of the Bits Per Transfer (BITS) field in MCSPI_CSR0. These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits in MCSPI_CSR0. Note that the fields BITS, CPOL and NCPHA of the other chip select registers (MCSPI_CSR1...MCSPI_CSR3) have no effect when the MCSPI is programmed in Client mode.

The bits are shifted out on the MISO line and sampled on the MOSI line.

When all bits are processed, the received data is transferred to MCSPI_RDR and the RDRF bit rises. If MCSPI_RDR has not been read before new data is received, the Overrun Error Status (OVRES) bit in MCSPI_SR is set. As long as this flag is set, data is loaded in MCSPI_RDR. The user must read MCSPI_SR to clear the OVRES bit.

When a transfer starts, the data shifted out is the data present in the internal shift register. If no data has been written in MCSPI_TDR, the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the internal shift register resets to 0.

When a first data is written in MCSPI_TDR, it is transferred immediately in the internal shift register and the TDRE flag rises. If new data is written, it remains in MCSPI_TDR until a transfer occurs, i.e., NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in MCSPI_TDR is transferred to the internal shift register and the TDRE flag rises. This enables frequent updates of critical variables with single transfers.

Then, new data is loaded in the internal shift register from MCSPI_TDR. If no character is ready to be transmitted, i.e., no character has been written in MCSPI_TDR since the last load from MCSPI_TDR to the internal shift register, MCSPI_TDR is retransmitted. In this case the Underrun Error Status Flag (UNDES) is set in MCSPI_SR.

If NSS rises between two characters, it must be kept high for two MCK clock periods or more and the next SPCK capture edge must not occur less than four MCK periods after NSS rises.

In Client mode, if the NSS line rises and the received character length does not match the configuration defined in MCSPI_CSR0.BITS, the Client Frame Error (SFERR) flag is set in MCSPI_SR.

The following figure shows a block diagram of the MCSPI when operating in Client mode.