47.7.2 Data Transfer
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the Clock Polarity (CPOL) bit in the MCSPI Chip Select registers (MCSPI_CSRx). The clock phase is programmed with the Clock Phase (NCPHA) bit in MCSPI_CSRx. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Consequently, a host/client pair must use the same parameter pair values to communicate. If multiple clients are connected and require different configurations, the host must reconfigure itself each time it needs to communicate with a different client.
The following table shows the four modes and corresponding parameter settings.
| MCSPI Mode | CPOL | NCPHA | Shift SPCK Edge | Capture SPCK Edge | SPCK Inactive Level |
|---|---|---|---|---|---|
| 0 | 0 | 1 | Falling | Rising | Low |
| 1 | 0 | 0 | Rising | Falling | Low |
| 2 | 1 | 1 | Rising | Falling | High |
| 3 | 1 | 0 | Falling | Rising | High |
Figure 47-3 and Figure 47-4 show examples of data transfers.