47.7.3 Host Mode Operations

When configured in Host mode, the MCSPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the client(s) connected to the SPI bus. The MCSPI drives the chip select line to the client and the serial clock signal (SPCK).

The MCSPI features two holding registers, the Transmit Data register (MCSPI_TDR) and the Receive Data register (MCSPI_RDR), and a single shift register. The holding registers maintain the data flow at a constant rate.

After enabling the MCSPI, a data transfer starts when the processor writes to MCSPI_TDR. The written data is immediately transferred into the internal shift register and the transfer on the MCSPI bus starts. While the data in the shift register is shifted on the MOSI line, the MISO line is sampled and shifted into the shift register. Data cannot be loaded in MCSPI_RDR without transmitting data. If there is no data to transmit, dummy data can be used (MCSPI_TDR filled with ones). If the Wait for Data Read Before Transfer (WDRBT) bit in MCSPI_MR is set, transmission can occur only if MCSPI_RDR has been read. If Receiving mode is not required, for example when communicating with a client receiver only (such as an LCD), the receive status flags in the MCSPI Status register (MCSPI_SR) can be discarded.

Before writing MCSPI_TDR, MCSPI_MR.PCS must be set in order to select a client.

If new data is written in MCSPI_TDR during the transfer, it is kept in MCSPI_TDR until the current transfer is completed. Then, the received data is transferred from the shift register to MCSPI_RDR, the data in MCSPI_TDR is loaded in the shift register and a new transfer starts.

As soon as MCSPI_TDR is written, the Transmit Data Register Empty (TDRE) flag in MCSPI_SR is cleared. When the data written in MCSPI_TDR is loaded into the shift register, MCSPI_SR.TDRE is set. The TDRE flag is used to trigger the Transmit PDC channel.

See the figure below.

The end of transfer is indicated by the Transmission Registers Empty (TXEMPTY) flag in MCSPI_SR. If a transfer delay (DLYBCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of this delay. The peripheral clock can be switched off at this time.

The transfer of received data from the internal shift register to MCSPI_RDR is indicated by the Receive Data Register Full (RDRF) bit in MCSPI_SR. When the received data is read, MCSPI_SR.RDRF is cleared.

If MCSPI_RDR was not read before new data is received, the Overrun Error (OVRES) flag in MCSPI_SR is set. As long as this flag is set, data is loaded in MCSPI_RDR. The user has to read MCSPI_SR to clear OVRES.

Figure 47-6 shows a block diagram of the MCSPI when operating in Host mode. Figure 47-7 shows a flow chart describing how transfers are handled.

The figure below shows the behavior of the TDRE, RDRF and TXEMPTY status flags within MCSPI_SR during an 8-bit data transfer in Fixed mode without the PDCinvolved.

The figure below shows the behavior of Transmission Register Empty (TXEMPTY), End of RX Buffer (ENDRX), End of TX Buffer (ENDTX), RX Buffer Full (RXBUFF) and TX Buffer Empty (TXBUFE) status flags within MCSPI_SR during an 8-bit data transfer in Fixed mode with the PDC involved. The PDC is programmed to transfer and receive three units of data. The next pointer and counter are not used. Flags RDRF and TDRE are not shown because they are managed by the PDC when using the PDC.