4.2.1 Device Configuration after a Power Cycle or General Reset

After a power cycle of all the power supply rails including VBAT, the system peripherals, such as the Flash controller, the Clock Generator, the Power Management Controller (PMC) and the SUPC, are in the following states prior to ROM code execution:

• Backup area is reset
• Slow Clock (SLCK) source is the internal 32 kHz RC Oscillator (32 kHz crystal oscillator is disabled)
• Main Clock (MAINCK) source is set to the 12 MHz internal RC Oscillator
• 12–48 MHz crystal oscillator and PLLs are disabled
• VDDCORE Supply Monitor and Core Reset are enabled
• VDD3V3 Supply Monitor is disabled
• Flash Wait State (FWS) bit in the Flash Mode register (EEFC_FMR) is set to 15 (0xF)
• Subsystem 1 is in Reset state and not clocked