35.6.5.3 SPI Mode Flow Diagram

Figure 35-9. SPI Mode Flow Diagram

The figure below shows Transmit Data Register Empty (TDRE), Receive Data Register Full (RDRF) and Transmission Register Empty (TXEMPTY) status flags behavior within the QSPI_SR during an 8-bit data transfer in Fixed mode, without PDC.

Figure 35-10. Status Register Flags Behavior

Note: Due to the internal architecture (see Block Diagram):

A latency occurs between the TXEMPTY rise and the end of the frame.
A delay occurs between the end of the frame and the RDRF flag rise.

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