35.6.5.5 Peripheral Deselection with PDC

When the PDC is used, the Chip Select line remains low during the transfer since the TDRE flag is managed by the PDC itself. Reloading the QSPI_TDR by the PDC is done as soon as the TDRE flag is set to one. In this case, setting the CSMODE field to 1 might not be needed. However, when other PDC channels connected to other peripherals are also in use, the QSPI PDC could be delayed by another PDC with a higher priority on the bus. Having PDC buffers in slower memories such as Flash memory or SDRAM compared to fast internal SRAM, may lengthen the reload time of the QSPI_TDR by the PDC as well. This means that the QSPI_TDR might not be reloaded in time to keep the chip select line low. In this case, the chip select line may toggle between data transfer and according to some SPI client devices, the communication might get lost. It may be necessary to configure the CSMODE field to 1.

When the CSMODE field is configured to 0, the QCS does not rise in all cases between two transfers on the same peripheral. During a transfer on a Chip Select, the flag TDRE rises as soon as the content of the QSPI_TDR is transferred into the internal shifter. When this flag is detected, the QSPI_TDR can be reloaded. If this reload occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the Chip Select is not de-asserted between the two transfers. This might lead to difficulties for interfacing with some serial peripherals requiring the chip select to be de-asserted after each transfer. To facilitate interfacing with such devices, the QSPI_MR can be programmed with the CSMODE field at 2.