34.10.6 USART Mode Register (OOK)
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
| Name: | FLEX_US_MR (OOK) |
| Offset: | 0x204 |
| Reset: | 0xC0000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FILTER | |||||||||
| Access | R/W | ||||||||
| Reset | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| OOKEN | OOKRXD | OVER | CLKO | MODE9 | MSBF | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | – | – | – | – | – | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CHMODE[1:0] | NBSTOP[1:0] | PAR[2:0] | SYNC | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHRL[1:0] | USCLKS[1:0] | USART_MODE[3:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | – | – | – | – | – | – | – | – | |
Bit 28 – FILTER Receive Line Filter
| Value | Description |
|---|---|
| 0 | The USART does not filter the receive line. |
| 1 | The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). |
Bit 21 – OOKEN OOK Modulation/Demodulation Enabled
| Value | Description |
|---|---|
| 0 | The OOK modulation and demodulation are disabled. |
| 1 | The TXD line is OOK modulated and RXD line is OOK demodulated. |
Bit 20 – OOKRXD OOK Demodulation Input Selection
| Value | Description |
|---|---|
| 0 | The OOK demodulation uses the output of the analog comparator. |
| 1 | The OOK demodulation uses the RXD line. |
Bit 19 – OVER Oversampling Mode
| Value | Description |
|---|---|
| 0 | 16x oversampling (recommended). |
| 1 | 8x oversampling. |
Bit 18 – CLKO Clock Output Select
| Value | Description |
|---|---|
| 0 | The USART does not drive the SCK pin. |
| 1 | The USART drives the SCK pin if USCLKS does not select the external clock SCK. |
Bit 17 – MODE9 9-bit Character Length
| Value | Description |
|---|---|
| 0 | CHRL defines character length. |
| 1 | 9-bit character length. |
Bit 16 – MSBF Bit Order
| Value | Description |
|---|---|
| 0 | Least significant bit is sent/received first. |
| 1 | Most significant bit is sent/received first. |
Bits 15:14 – CHMODE[1:0] Channel Mode
| Value | Name | Description |
|---|---|---|
| 0 | NORMAL | Normal mode |
| 1 | AUTOMATIC | Automatic Echo. Receiver input is connected to the TXD pin. |
| 2 | LOCAL_LOOPBACK | Local Loopback. Transmitter output is connected to the Receiver Input. |
| 3 | REMOTE_LOOPBACK | Remote Loopback. RXD pin is internally connected to the TXD pin. |
Bits 13:12 – NBSTOP[1:0] Number of Stop Bits
| Value | Name | Description |
|---|---|---|
| 0 | 1_BIT | 1 stop bit |
| 1 | 1_5_BIT | 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) |
| 2 | 2_BIT | 2 stop bits |
Bits 11:9 – PAR[2:0] Parity Type
| Value | Name | Description |
|---|---|---|
| 0 | EVEN | Even parity |
| 1 | ODD | Odd parity |
| 2 | SPACE | Parity forced to 0 (Space) |
| 3 | MARK | Parity forced to 1 (Mark) |
| 4 | NO | No parity |
| 6 | MULTIDROP | Multidrop mode |
Bit 8 – SYNC Synchronous Mode Select
| Value | Description |
|---|---|
| 0 | USART operates in Asynchronous mode. |
| 1 | USART operates in Synchronous mode. |
Bits 7:6 – CHRL[1:0] Character Length
| Value | Name | Description |
|---|---|---|
| 0 | 5_BIT | Character length is 5 bits |
| 1 | 6_BIT | Character length is 6 bits |
| 2 | 7_BIT | Character length is 7 bits |
| 3 | 8_BIT | Character length is 8 bits |
Bits 5:4 – USCLKS[1:0] Clock Selection
| Value | Name | Description |
|---|---|---|
| 0 | MCK | Peripheral clock is selected |
| 1 | DIV | Peripheral clock divided (DIV = 8) is selected |
| 2 | PCK | PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. |
| 3 | SCK | Serial clock (SCK) is selected. |
Bits 3:0 – USART_MODE[3:0] USART Mode of Operation
PDC transfers are supported in all USART modes of operation.
| Value | Name | Description |
|---|---|---|
| 0x0 | NORMAL | Normal mode |