34.10.9 USART Interrupt Disable Register

For LIN-specific configurations, see USART Interrupt Disable Register (LIN_MODE).

This register can only be written if the WPITEN bit is cleared in the USART Write Protection Mode Register.

The following configuration values are valid for all listed bit names of this register:

0: No effect

1: Disables the corresponding interrupt.

Name: FLEX_US_IDR
Offset: 0x20C
Reset: –
Property: Write-only

Bit 3130292827262524 
        MANE 
Access W 
Reset – 
Bit 2322212019181716 
  CMP  CTSIC    
Access WW 
Reset –– 
Bit 15141312111098 
   NACKRXBUFFTXBUFEITERTXEMPTYTIMEOUT 
Access WWWWWW 
Reset –––––– 
Bit 76543210 
 PAREFRAMEOVREENDTXENDRXRXBRKTXRDYRXRDY 
Access WWWWWWWW 
Reset –––––––– 

Bit 24 – MANE Manchester Error Interrupt Disable

Bit 22 – CMP Comparison Interrupt Disable

Bit 19 – CTSIC Clear to Send Input Change Interrupt Disable

Bit 13 – NACK Non Acknowledge Interrupt Disable

Bit 12 – RXBUFF Buffer Full Interrupt Disable (available in all USART modes of operation)

Bit 11 – TXBUFE Buffer Empty Interrupt Disable (available in all USART modes of operation)

Bit 10 – ITER Max Number of Repetitions Reached Interrupt Disable

Bit 9 – TXEMPTY TXEMPTY Interrupt Disable

Bit 8 – TIMEOUT Timeout Interrupt Disable

Bit 7 – PARE Parity Error Interrupt Disable

Bit 6 – FRAME Framing Error Interrupt Disable

Bit 5 – OVRE Overrun Error Interrupt Disable

Bit 4 – ENDTX End of Transmit Interrupt Disable (available in all USART modes of operation)

Bit 3 – ENDRX End of Receive Transfer Interrupt Disable (available in all USART modes of operation)

Bit 2 – RXBRK Receiver Break Interrupt Disable

Bit 1 – TXRDY TXRDY Interrupt Disable

Bit 0 – RXRDY RXRDY Interrupt Disable